mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-06 23:32:27 +00:00
Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145483 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
553fe05f23
commit
316cd2a2c5
@ -309,32 +309,32 @@ void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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Src1Name = getRegName(MI->getOperand(1).getReg());
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// FALL THROUGH.
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case X86::VPERMILPSmi:
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DecodeVPERMILPSMask(4, MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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DecodeVPERMILPMask(MVT::v4f32, MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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DestName = getRegName(MI->getOperand(0).getReg());
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break;
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case X86::VPERMILPSYri:
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Src1Name = getRegName(MI->getOperand(1).getReg());
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// FALL THROUGH.
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case X86::VPERMILPSYmi:
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DecodeVPERMILPSMask(8, MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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DecodeVPERMILPMask(MVT::v8f32, MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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DestName = getRegName(MI->getOperand(0).getReg());
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break;
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case X86::VPERMILPDri:
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Src1Name = getRegName(MI->getOperand(1).getReg());
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// FALL THROUGH.
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case X86::VPERMILPDmi:
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DecodeVPERMILPDMask(2, MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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DecodeVPERMILPMask(MVT::v2f64, MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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DestName = getRegName(MI->getOperand(0).getReg());
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break;
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case X86::VPERMILPDYri:
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Src1Name = getRegName(MI->getOperand(1).getReg());
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// FALL THROUGH.
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case X86::VPERMILPDYmi:
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DecodeVPERMILPDMask(4, MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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DecodeVPERMILPMask(MVT::v4f64, MI->getOperand(MI->getNumOperands()-1).getImm(),
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ShuffleMask);
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DestName = getRegName(MI->getOperand(0).getReg());
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break;
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case X86::VPERM2F128rr:
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@ -193,36 +193,23 @@ void DecodeUNPCKLPMask(EVT VT, SmallVectorImpl<unsigned> &ShuffleMask) {
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}
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}
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// DecodeVPERMILPSMask - Decodes VPERMILPS permutes for any 128-bit 32-bit
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// elements. For 256-bit vectors, it's considered as two 128 lanes, the
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// referenced elements can't cross lanes and the mask of the first lane must
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// be the same of the second.
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void DecodeVPERMILPSMask(unsigned NumElts, unsigned Imm,
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SmallVectorImpl<unsigned> &ShuffleMask) {
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unsigned NumLanes = (NumElts*32)/128;
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unsigned LaneSize = NumElts/NumLanes;
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// DecodeVPERMILPMask - Decodes VPERMILPS/ VPERMILPD permutes for any 128-bit
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// 32-bit or 64-bit elements. For 256-bit vectors, it's considered as two 128
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// lanes. For VPERMILPS, referenced elements can't cross lanes and the mask of
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// the first lane must be the same of the second.
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void DecodeVPERMILPMask(EVT VT, unsigned Imm,
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SmallVectorImpl<unsigned> &ShuffleMask) {
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unsigned NumElts = VT.getVectorNumElements();
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unsigned NumLanes = VT.getSizeInBits() / 128;
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unsigned NumLaneElts = NumElts / NumLanes;
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for (unsigned l = 0; l != NumLanes; ++l) {
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for (unsigned i = 0; i != LaneSize; ++i) {
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unsigned Idx = (Imm >> (i*2)) & 0x3 ;
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ShuffleMask.push_back(Idx+(l*LaneSize));
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}
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}
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}
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// DecodeVPERMILPDMask - Decodes VPERMILPD permutes for any 128-bit 64-bit
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// elements. For 256-bit vectors, it's considered as two 128 lanes, the
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// referenced elements can't cross lanes but the mask of the first lane can
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// be the different of the second (not like VPERMILPS).
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void DecodeVPERMILPDMask(unsigned NumElts, unsigned Imm,
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SmallVectorImpl<unsigned> &ShuffleMask) {
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unsigned NumLanes = (NumElts*64)/128;
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unsigned LaneSize = NumElts/NumLanes;
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for (unsigned l = 0; l < NumLanes; ++l) {
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for (unsigned i = l*LaneSize; i < LaneSize*(l+1); ++i) {
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unsigned Idx = (Imm >> i) & 0x1;
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ShuffleMask.push_back(Idx+(l*LaneSize));
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unsigned LaneStart = l*NumLaneElts;
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for (unsigned i = 0; i != NumLaneElts; ++i) {
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unsigned Idx = NumLaneElts == 4 ? (Imm >> (i*2)) & 0x3
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: (Imm >> (i+LaneStart)) & 0x1;
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ShuffleMask.push_back(Idx+LaneStart);
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}
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}
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}
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@ -78,18 +78,11 @@ void DecodeUNPCKHPMask(EVT VT, SmallVectorImpl<unsigned> &ShuffleMask);
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void DecodeUNPCKLPMask(EVT VT, SmallVectorImpl<unsigned> &ShuffleMask);
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// DecodeVPERMILPSMask - Decodes VPERMILPS permutes for any 128-bit 32-bit
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// elements. For 256-bit vectors, it's considered as two 128 lanes, the
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// referenced elements can't cross lanes and the mask of the first lane must
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// be the same of the second.
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void DecodeVPERMILPSMask(unsigned NElts, unsigned Imm,
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SmallVectorImpl<unsigned> &ShuffleMask);
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// DecodeVPERMILPDMask - Decodes VPERMILPD permutes for any 128-bit 64-bit
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// elements. For 256-bit vectors, it's considered as two 128 lanes, the
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// referenced elements can't cross lanes but the mask of the first lane can
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// be the different of the second (not like VPERMILPS).
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void DecodeVPERMILPDMask(unsigned NElts, unsigned Imm,
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// DecodeVPERMILPMask - Decodes VPERMILPS/ VPERMILPD permutes for any 128-bit
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// 32-bit or 64-bit elements. For 256-bit vectors, it's considered as two 128
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// lanes. For VPERMILPS, referenced elements can't cross lanes and the mask of
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// the first lane must be the same of the second.
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void DecodeVPERMILPMask(EVT VT, unsigned Imm,
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SmallVectorImpl<unsigned> &ShuffleMask);
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void DecodeVPERM2F128Mask(unsigned Imm,
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@ -2847,8 +2847,7 @@ static bool isTargetShuffle(unsigned Opcode) {
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case X86ISD::PUNPCKL:
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case X86ISD::UNPCKHP:
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case X86ISD::PUNPCKH:
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case X86ISD::VPERMILPS:
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case X86ISD::VPERMILPD:
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case X86ISD::VPERMILP:
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case X86ISD::VPERM2F128:
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case X86ISD::VPERM2I128:
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return true;
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@ -2876,8 +2875,7 @@ static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
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case X86ISD::PSHUFD:
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case X86ISD::PSHUFHW:
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case X86ISD::PSHUFLW:
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case X86ISD::VPERMILPS:
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case X86ISD::VPERMILPD:
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case X86ISD::VPERMILP:
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return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
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}
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@ -4613,14 +4611,9 @@ static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
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return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
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Depth+1);
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}
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case X86ISD::VPERMILPS:
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case X86ISD::VPERMILP:
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ImmN = N->getOperand(N->getNumOperands()-1);
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DecodeVPERMILPSMask(NumElems, cast<ConstantSDNode>(ImmN)->getZExtValue(),
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ShuffleMask);
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break;
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case X86ISD::VPERMILPD:
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ImmN = N->getOperand(N->getNumOperands()-1);
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DecodeVPERMILPDMask(NumElems, cast<ConstantSDNode>(ImmN)->getZExtValue(),
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DecodeVPERMILPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
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ShuffleMask);
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break;
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case X86ISD::VPERM2F128:
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@ -6528,22 +6521,6 @@ static inline unsigned getUNPCKHOpcode(EVT VT, bool HasAVX2) {
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return 0;
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}
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static inline unsigned getVPERMILOpcode(EVT VT) {
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switch(VT.getSimpleVT().SimpleTy) {
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case MVT::v4i32:
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case MVT::v4f32:
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case MVT::v8i32:
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case MVT::v8f32: return X86ISD::VPERMILPS;
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case MVT::v2i64:
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case MVT::v2f64:
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case MVT::v4i64:
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case MVT::v4f64: return X86ISD::VPERMILPD;
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default:
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llvm_unreachable("Unknown type for vpermil");
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}
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return 0;
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}
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static inline unsigned getVPERM2X128Opcode(EVT VT, bool HasAVX2) {
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switch(VT.getSimpleVT().SimpleTy) {
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case MVT::v32i8:
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@ -6876,7 +6853,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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// Handle VPERMILPS/D* permutations
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if (isVPERMILPMask(M, VT, Subtarget->hasAVX()))
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return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
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return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
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getShuffleVPERMILPImmediate(SVOp), DAG);
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// Handle VPERM2F128/VPERM2I128 permutations
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@ -11179,8 +11156,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::PUNPCKL: return "X86ISD::PUNPCKL";
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case X86ISD::PUNPCKH: return "X86ISD::PUNPCKH";
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case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
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case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS";
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case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD";
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case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
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case X86ISD::VPERM2F128: return "X86ISD::VPERM2F128";
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case X86ISD::VPERM2I128: return "X86ISD::VPERM2I128";
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case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
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@ -14767,8 +14743,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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case X86ISD::PSHUFLW:
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case X86ISD::MOVSS:
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case X86ISD::MOVSD:
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case X86ISD::VPERMILPS:
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case X86ISD::VPERMILPD:
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case X86ISD::VPERMILP:
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case X86ISD::VPERM2F128:
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case X86ISD::VPERM2I128:
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case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
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@ -277,8 +277,7 @@ namespace llvm {
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UNPCKHP,
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PUNPCKL,
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PUNPCKH,
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VPERMILPS,
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VPERMILPD,
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VPERMILP,
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VPERM2F128,
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VPERM2I128,
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VBROADCAST,
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@ -136,8 +136,7 @@ def X86Unpckhp : SDNode<"X86ISD::UNPCKHP", SDTShuff2Op>;
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def X86Punpckl : SDNode<"X86ISD::PUNPCKL", SDTShuff2Op>;
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def X86Punpckh : SDNode<"X86ISD::PUNPCKH", SDTShuff2Op>;
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def X86VPermilps : SDNode<"X86ISD::VPERMILPS", SDTShuff2OpI>;
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def X86VPermilpd : SDNode<"X86ISD::VPERMILPD", SDTShuff2OpI>;
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def X86VPermilp : SDNode<"X86ISD::VPERMILP", SDTShuff2OpI>;
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def X86VPerm2f128 : SDNode<"X86ISD::VPERM2F128", SDTShuff3OpI>;
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def X86VPerm2i128 : SDNode<"X86ISD::VPERM2I128", SDTShuff3OpI>;
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@ -7164,31 +7164,6 @@ def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
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def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
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(VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
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def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
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(i32 imm)),
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(VINSERTF128rr VR256:$src1, VR128:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
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(i32 imm)),
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(VINSERTF128rr VR256:$src1, VR128:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
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(i32 imm)),
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(VINSERTF128rr VR256:$src1, VR128:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
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(i32 imm)),
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(VINSERTF128rr VR256:$src1, VR128:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
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(i32 imm)),
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(VINSERTF128rr VR256:$src1, VR128:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
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(i32 imm)),
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(VINSERTF128rr VR256:$src1, VR128:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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//===----------------------------------------------------------------------===//
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// VEXTRACTF128 - Extract packed floating-point values
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//
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@ -7211,31 +7186,6 @@ def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
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def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
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(VEXTRACTF128rr VR256:$src1, imm:$src2)>;
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
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(v4f32 (VEXTRACTF128rr
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(v8f32 VR256:$src1),
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(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
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(v2f64 (VEXTRACTF128rr
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(v4f64 VR256:$src1),
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(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
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(v4i32 (VEXTRACTF128rr
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(v8i32 VR256:$src1),
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(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
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(v2i64 (VEXTRACTF128rr
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(v4i64 VR256:$src1),
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(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
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(v8i16 (VEXTRACTF128rr
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(v16i16 VR256:$src1),
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(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
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def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
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(v16i8 (VEXTRACTF128rr
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(v32i8 VR256:$src1),
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(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
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//===----------------------------------------------------------------------===//
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// VMASKMOV - Conditional SIMD Packed Loads and Stores
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//
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@ -7322,22 +7272,22 @@ let ExeDomain = SSEPackedDouble in {
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int_x86_avx_vpermil_pd_256>;
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}
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def : Pat<(v8f32 (X86VPermilps VR256:$src1, (i8 imm:$imm))),
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def : Pat<(v8f32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
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(VPERMILPSYri VR256:$src1, imm:$imm)>;
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def : Pat<(v4f64 (X86VPermilpd VR256:$src1, (i8 imm:$imm))),
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def : Pat<(v4f64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
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(VPERMILPDYri VR256:$src1, imm:$imm)>;
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def : Pat<(v8i32 (X86VPermilps VR256:$src1, (i8 imm:$imm))),
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def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
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(VPERMILPSYri VR256:$src1, imm:$imm)>;
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def : Pat<(v4i64 (X86VPermilpd VR256:$src1, (i8 imm:$imm))),
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def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
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(VPERMILPDYri VR256:$src1, imm:$imm)>;
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def : Pat<(v8f32 (X86VPermilps (memopv8f32 addr:$src1), (i8 imm:$imm))),
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def : Pat<(v8f32 (X86VPermilp (memopv8f32 addr:$src1), (i8 imm:$imm))),
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(VPERMILPSYmi addr:$src1, imm:$imm)>;
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def : Pat<(v4f64 (X86VPermilpd (memopv4f64 addr:$src1), (i8 imm:$imm))),
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def : Pat<(v4f64 (X86VPermilp (memopv4f64 addr:$src1), (i8 imm:$imm))),
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(VPERMILPDYmi addr:$src1, imm:$imm)>;
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def : Pat<(v8i32 (X86VPermilps (bc_v8i32 (memopv4i64 addr:$src1)),
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def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
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(i8 imm:$imm))),
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(VPERMILPSYmi addr:$src1, imm:$imm)>;
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def : Pat<(v4i64 (X86VPermilpd (memopv4i64 addr:$src1), (i8 imm:$imm))),
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def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
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(VPERMILPDYmi addr:$src1, imm:$imm)>;
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//===----------------------------------------------------------------------===//
|
||||
@ -7656,6 +7606,51 @@ def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
|
||||
(int_x86_avx2_vinserti128 VR256:$src1, (memopv2i64 addr:$src2),
|
||||
imm:$src3))]>, VEX_4V;
|
||||
|
||||
let Predicates = [HasAVX2] in {
|
||||
def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
|
||||
(i32 imm)),
|
||||
(VINSERTI128rr VR256:$src1, VR128:$src2,
|
||||
(INSERT_get_vinsertf128_imm VR256:$ins))>;
|
||||
def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
|
||||
(i32 imm)),
|
||||
(VINSERTI128rr VR256:$src1, VR128:$src2,
|
||||
(INSERT_get_vinsertf128_imm VR256:$ins))>;
|
||||
def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
|
||||
(i32 imm)),
|
||||
(VINSERTI128rr VR256:$src1, VR128:$src2,
|
||||
(INSERT_get_vinsertf128_imm VR256:$ins))>;
|
||||
def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
|
||||
(i32 imm)),
|
||||
(VINSERTI128rr VR256:$src1, VR128:$src2,
|
||||
(INSERT_get_vinsertf128_imm VR256:$ins))>;
|
||||
}
|
||||
|
||||
// AVX1 patterns
|
||||
def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
|
||||
(i32 imm)),
|
||||
(VINSERTF128rr VR256:$src1, VR128:$src2,
|
||||
(INSERT_get_vinsertf128_imm VR256:$ins))>;
|
||||
def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
|
||||
(i32 imm)),
|
||||
(VINSERTF128rr VR256:$src1, VR128:$src2,
|
||||
(INSERT_get_vinsertf128_imm VR256:$ins))>;
|
||||
def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
|
||||
(i32 imm)),
|
||||
(VINSERTF128rr VR256:$src1, VR128:$src2,
|
||||
(INSERT_get_vinsertf128_imm VR256:$ins))>;
|
||||
def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
|
||||
(i32 imm)),
|
||||
(VINSERTF128rr VR256:$src1, VR128:$src2,
|
||||
(INSERT_get_vinsertf128_imm VR256:$ins))>;
|
||||
def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
|
||||
(i32 imm)),
|
||||
(VINSERTF128rr VR256:$src1, VR128:$src2,
|
||||
(INSERT_get_vinsertf128_imm VR256:$ins))>;
|
||||
def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
|
||||
(i32 imm)),
|
||||
(VINSERTF128rr VR256:$src1, VR128:$src2,
|
||||
(INSERT_get_vinsertf128_imm VR256:$ins))>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// VEXTRACTI128 - Extract packed integer values
|
||||
//
|
||||
@ -7670,6 +7665,51 @@ def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
|
||||
(ins i128mem:$dst, VR256:$src1, i8imm:$src2),
|
||||
"vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
|
||||
|
||||
let Predicates = [HasAVX2] in {
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
|
||||
(v2i64 (VEXTRACTI128rr
|
||||
(v4i64 VR256:$src1),
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
|
||||
(v4i32 (VEXTRACTI128rr
|
||||
(v8i32 VR256:$src1),
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
|
||||
(v8i16 (VEXTRACTI128rr
|
||||
(v16i16 VR256:$src1),
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
|
||||
(v16i8 (VEXTRACTI128rr
|
||||
(v32i8 VR256:$src1),
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
|
||||
}
|
||||
|
||||
// AVX1 patterns
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
|
||||
(v4f32 (VEXTRACTF128rr
|
||||
(v8f32 VR256:$src1),
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
|
||||
(v2f64 (VEXTRACTF128rr
|
||||
(v4f64 VR256:$src1),
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
|
||||
(v2i64 (VEXTRACTF128rr
|
||||
(v4i64 VR256:$src1),
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
|
||||
(v4i32 (VEXTRACTF128rr
|
||||
(v8i32 VR256:$src1),
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
|
||||
(v8i16 (VEXTRACTF128rr
|
||||
(v16i16 VR256:$src1),
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
|
||||
def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
|
||||
(v16i8 (VEXTRACTF128rr
|
||||
(v32i8 VR256:$src1),
|
||||
(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
|
||||
//
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user