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Use aligned load/store instructions for spilling Q registers when we know the stack slot is 128 bit aligned

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86425 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2009-11-08 00:27:19 +00:00
parent fdc834046e
commit 31bc849123
2 changed files with 25 additions and 8 deletions
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29
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -667,12 +667,13 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
if (I != MBB.end()) DL = I->getDebugLoc();
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = *MF.getFrameInfo();
unsigned Align = MFI.getObjectAlignment(FI);
MachineMemOperand *MMO =
MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
MachineMemOperand::MOStore, 0,
MFI.getObjectSize(FI),
MFI.getObjectAlignment(FI));
Align);
if (RC == ARM::GPRRegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
@ -692,8 +693,16 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
assert((RC == ARM::QPRRegisterClass ||
RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
// FIXME: Neon instructions should support predicates
BuildMI(MBB, I, DL, get(ARM::VSTRQ)).addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
if (Align >= 16
&& (getRegisterInfo().needsStackRealignment(MF))) {
BuildMI(MBB, I, DL, get(ARM::VST1q64))
.addFrameIndex(FI).addImm(0).addImm(0).addImm(128).addMemOperand(MMO)
.addReg(SrcReg, getKillRegState(isKill));
} else {
BuildMI(MBB, I, DL, get(ARM::VSTRQ)).
addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
}
}
}
@ -705,12 +714,13 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
if (I != MBB.end()) DL = I->getDebugLoc();
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = *MF.getFrameInfo();
unsigned Align = MFI.getObjectAlignment(FI);
MachineMemOperand *MMO =
MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
MachineMemOperand::MOLoad, 0,
MFI.getObjectSize(FI),
MFI.getObjectAlignment(FI));
Align);
if (RC == ARM::GPRRegisterClass) {
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
@ -728,8 +738,15 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
RC == ARM::QPR_VFP2RegisterClass ||
RC == ARM::QPR_8RegisterClass) && "Unknown regclass!");
// FIXME: Neon instructions should support predicates
BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0).
addMemOperand(MMO);
if (Align >= 16
&& (getRegisterInfo().needsStackRealignment(MF))) {
BuildMI(MBB, I, DL, get(ARM::VLD1q64))
.addReg(DestReg)
.addFrameIndex(FI).addImm(0).addImm(0).addImm(128).addMemOperand(MMO);
} else {
BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0).
addMemOperand(MMO);
}
}
}

4
lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -520,7 +520,6 @@ needsStackRealignment(const MachineFunction &MF) const {
// unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
return (RealignStack &&
!AFI->isThumb1OnlyFunction() &&
AFI->hasStackFrame() &&
// (MFI->getMaxAlignment() > StackAlign) &&
!MFI->hasVarSizedObjects());
}
@ -529,7 +528,8 @@ bool ARMBaseRegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const
const MachineFrameInfo *MFI = MF.getFrameInfo();
if (NoFramePointerElim && MFI->hasCalls())
return true;
return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
|| needsStackRealignment(MF);
}
/// estimateStackSize - Estimate and return the size of the frame.