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https://github.com/c64scene-ar/llvm-6502.git
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Migrage PPCRegisterInfo to use the cached subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227546 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
parent
e413c8afe0
commit
31f58f2c74
@ -164,8 +164,8 @@ void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
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BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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const PPCFrameLowering *PPCFI = static_cast<const PPCFrameLowering *>(
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MF.getSubtarget().getFrameLowering());
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const PPCFrameLowering *PPCFI =
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static_cast<const PPCFrameLowering *>(Subtarget.getFrameLowering());
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// The ZERO register is not really a register, but the representation of r0
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// when used in instructions that treat r0 as the constant 0.
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@ -244,10 +244,9 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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return Reserved;
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}
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unsigned
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PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
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unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const {
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const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
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const unsigned DefaultSafety = 1;
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switch (RC->getID()) {
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@ -275,8 +274,8 @@ PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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}
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}
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const TargetRegisterClass*
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PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)const {
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const TargetRegisterClass *PPCRegisterInfo::getLargestLegalSuperClass(
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const TargetRegisterClass *RC) const {
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if (Subtarget.hasVSX()) {
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// With VSX, we can inflate various sub-register classes to the full VSX
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// register set.
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@ -311,7 +310,7 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
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// Get the frame info.
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MachineFrameInfo *MFI = MF.getFrameInfo();
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// Get the instruction info.
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
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// Determine whether 64-bit pointers are used.
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bool LP64 = Subtarget.isPPC64();
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DebugLoc dl = MI.getDebugLoc();
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@ -322,10 +321,7 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
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unsigned FrameSize = MFI->getStackSize();
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// Get stack alignments.
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unsigned TargetAlign = MF.getTarget()
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.getSubtargetImpl()
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->getFrameLowering()
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->getStackAlignment();
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unsigned TargetAlign = Subtarget.getFrameLowering()->getStackAlignment();
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unsigned MaxAlign = MFI->getMaxAlignment();
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assert((maxCallFrameSize & (MaxAlign-1)) == 0 &&
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"Maximum call-frame size not sufficiently aligned");
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@ -430,7 +426,7 @@ void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
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DebugLoc dl = MI.getDebugLoc();
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bool LP64 = Subtarget.isPPC64();
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@ -474,7 +470,7 @@ void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
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DebugLoc dl = MI.getDebugLoc();
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bool LP64 = Subtarget.isPPC64();
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@ -547,7 +543,7 @@ void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
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DebugLoc dl = MI.getDebugLoc();
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bool LP64 = Subtarget.isPPC64();
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@ -590,7 +586,7 @@ void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II,
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
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DebugLoc dl = MI.getDebugLoc();
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bool LP64 = Subtarget.isPPC64();
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@ -637,7 +633,7 @@ void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II,
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
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DebugLoc dl = MI.getDebugLoc();
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const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
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@ -662,7 +658,7 @@ void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
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DebugLoc dl = MI.getDebugLoc();
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const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
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@ -745,7 +741,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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// Get the basic block's function.
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MachineFunction &MF = *MBB.getParent();
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// Get the instruction info.
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
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// Get the frame info.
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MachineFrameInfo *MFI = MF.getFrameInfo();
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DebugLoc dl = MI.getDebugLoc();
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@ -873,7 +869,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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}
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unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
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const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
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if (!Subtarget.isPPC64())
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return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
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@ -917,10 +913,7 @@ bool PPCRegisterInfo::canRealignStack(const MachineFunction &MF) const {
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bool PPCRegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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const Function *F = MF.getFunction();
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unsigned StackAlign = MF.getTarget()
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.getSubtargetImpl()
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->getFrameLowering()
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->getStackAlignment();
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unsigned StackAlign = Subtarget.getFrameLowering()->getStackAlignment();
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bool requiresRealignment =
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((MFI->getMaxAlignment() > StackAlign) ||
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F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
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@ -958,8 +951,8 @@ needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
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MachineBasicBlock &MBB = *MI->getParent();
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MachineFunction &MF = *MBB.getParent();
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const PPCFrameLowering *PPCFI = static_cast<const PPCFrameLowering *>(
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MF.getSubtarget().getFrameLowering());
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const PPCFrameLowering *PPCFI =
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static_cast<const PPCFrameLowering *>(Subtarget.getFrameLowering());
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unsigned StackEst =
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PPCFI->determineFrameLayout(MF, false, true);
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@ -993,7 +986,7 @@ materializeFrameBaseRegister(MachineBasicBlock *MBB,
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DL = Ins->getDebugLoc();
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const MachineFunction &MF = *MBB->getParent();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
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const MCInstrDesc &MCID = TII.get(ADDriOpc);
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MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
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@ -1018,7 +1011,7 @@ void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
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const MCInstrDesc &MCID = MI.getDesc();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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MRI.constrainRegClass(BaseReg,
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