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[mips] Support SELECT nodes for targets that don't have conditional-move instructions.
Summary: For Mips targets that do not have conditional-move instructions, ie. targets before MIPS32 and MIPS-IV, we have to insert a diamond control-flow pattern in order to support SELECT nodes. In order to do that, we add pseudo-instructions with a custom inserter that emits the necessary control-flow that selects the correct value. With this patch we add complete support for code generation of Mips-II targets based on the LLVM test-suite. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6212 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224124 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vasileios Kalintiris
@@ -263,3 +263,34 @@ defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
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FGR_64;
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defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>, INSN_MIPS4_32_NOT_32R6_64R6,
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FGR_64;
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// For targets that don't have conditional-move instructions
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// we have to match SELECT nodes with pseudo instructions.
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let usesCustomInserter = 1 in {
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class Select_Pseudo<RegisterOperand RC> :
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PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
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[(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>,
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ISA_MIPS1_NOT_4_32;
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class SelectFP_Pseudo_T<RegisterOperand RC> :
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PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
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[(set RC:$dst, (MipsCMovFP_T RC:$T, GPR32Opnd:$cond, RC:$F))]>,
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ISA_MIPS1_NOT_4_32;
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class SelectFP_Pseudo_F<RegisterOperand RC> :
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PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F),
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[(set RC:$dst, (MipsCMovFP_F RC:$T, GPR32Opnd:$cond, RC:$F))]>,
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ISA_MIPS1_NOT_4_32;
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}
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def PseudoSELECT_I : Select_Pseudo<GPR32Opnd>;
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def PseudoSELECT_S : Select_Pseudo<FGR32Opnd>;
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def PseudoSELECT_D32 : Select_Pseudo<AFGR64Opnd>;
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def PseudoSELECTFP_T_I : SelectFP_Pseudo_T<GPR32Opnd>;
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def PseudoSELECTFP_T_S : SelectFP_Pseudo_T<FGR32Opnd>;
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def PseudoSELECTFP_T_D32 : SelectFP_Pseudo_T<AFGR64Opnd>;
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def PseudoSELECTFP_F_I : SelectFP_Pseudo_F<GPR32Opnd>;
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def PseudoSELECTFP_F_S : SelectFP_Pseudo_F<FGR32Opnd>;
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def PseudoSELECTFP_F_D32 : SelectFP_Pseudo_F<AFGR64Opnd>;
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@@ -945,6 +945,19 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MI, *BB, *getTargetMachine().getSubtargetImpl()->getInstrInfo(), true);
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case Mips::SEL_D:
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return emitSEL_D(MI, BB);
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case Mips::PseudoSELECT_I:
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case Mips::PseudoSELECT_S:
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case Mips::PseudoSELECT_D32:
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return emitPseudoSELECT(MI, BB, false, Mips::BNE);
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case Mips::PseudoSELECTFP_F_I:
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case Mips::PseudoSELECTFP_F_S:
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case Mips::PseudoSELECTFP_F_D32:
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return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
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case Mips::PseudoSELECTFP_T_I:
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case Mips::PseudoSELECTFP_T_S:
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case Mips::PseudoSELECTFP_T_D32:
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return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
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}
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}
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@@ -3736,3 +3749,80 @@ void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
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State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
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}
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MachineBasicBlock *
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MipsTargetLowering::emitPseudoSELECT(MachineInstr *MI, MachineBasicBlock *BB,
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bool isFPCmp, unsigned Opc) const {
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assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
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"Subtarget already supports SELECT nodes with the use of"
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"conditional-move instructions.");
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const TargetInstrInfo *TII =
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getTargetMachine().getSubtargetImpl()->getInstrInfo();
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DebugLoc DL = MI->getDebugLoc();
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// To "insert" a SELECT instruction, we actually have to insert the
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// diamond control-flow pattern. The incoming instruction knows the
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// destination vreg to set, the condition code register to branch on, the
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// true/false values to select between, and a branch opcode to use.
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction::iterator It = BB;
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++It;
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// thisMBB:
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// ...
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// TrueVal = ...
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// setcc r1, r2, r3
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// bNE r1, r0, copy1MBB
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// fallthrough --> copy0MBB
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MachineBasicBlock *thisMBB = BB;
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MachineFunction *F = BB->getParent();
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MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
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F->insert(It, copy0MBB);
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F->insert(It, sinkMBB);
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// Transfer the remainder of BB and its successor edges to sinkMBB.
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sinkMBB->splice(sinkMBB->begin(), BB,
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std::next(MachineBasicBlock::iterator(MI)), BB->end());
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sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
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// Next, add the true and fallthrough blocks as its successors.
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BB->addSuccessor(copy0MBB);
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BB->addSuccessor(sinkMBB);
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if (isFPCmp) {
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// bc1[tf] cc, sinkMBB
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BuildMI(BB, DL, TII->get(Opc))
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.addReg(MI->getOperand(1).getReg())
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.addMBB(sinkMBB);
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} else {
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// bne rs, $0, sinkMBB
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BuildMI(BB, DL, TII->get(Opc))
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.addReg(MI->getOperand(1).getReg())
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.addReg(Mips::ZERO)
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.addMBB(sinkMBB);
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}
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// copy0MBB:
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// %FalseValue = ...
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// # fallthrough to sinkMBB
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BB = copy0MBB;
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// Update machine-CFG edges
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BB->addSuccessor(sinkMBB);
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// sinkMBB:
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// %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
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// ...
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BB = sinkMBB;
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BuildMI(*BB, BB->begin(), DL,
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TII->get(Mips::PHI), MI->getOperand(0).getReg())
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.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
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.addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB);
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MI->eraseFromParent(); // The pseudo instruction is gone now.
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return BB;
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}
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@@ -534,6 +534,9 @@ namespace llvm {
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MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
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MachineBasicBlock *BB, unsigned Size) const;
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MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const;
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MachineBasicBlock *emitPseudoSELECT(MachineInstr *MI,
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MachineBasicBlock *BB, bool isFPCmp,
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unsigned Opc) const;
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};
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/// Create MipsTargetLowering objects.
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@@ -156,6 +156,8 @@ def HasMips3 : Predicate<"Subtarget->hasMips3()">,
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AssemblerPredicate<"FeatureMips3">;
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def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">,
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AssemblerPredicate<"FeatureMips4_32">;
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def NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">,
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AssemblerPredicate<"FeatureMips4_32">;
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def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">,
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AssemblerPredicate<"FeatureMips4_32r2">;
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def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">,
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@@ -220,6 +222,9 @@ class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
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// subtractive predicate will hopefully keep us under the 32 predicate
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// limit long enough to develop an alternative way to handle P1||P2
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// predicates.
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class ISA_MIPS1_NOT_4_32 {
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list<Predicate> InsnPredicates = [NotMips4_32];
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}
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class ISA_MIPS1_NOT_32R6_64R6 {
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list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
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}
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649
test/CodeGen/Mips/llvm-ir/select.ll
Normal file
649
test/CodeGen/Mips/llvm-ir/select.ll
Normal file
@@ -0,0 +1,649 @@
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; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=M2
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; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV \
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; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R1
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; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV \
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; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2
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; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
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; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
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; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
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; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
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define signext i1 @tst_select_i1_i1(i1 signext %s,
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i1 signext %x, i1 signext %y) {
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entry:
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; ALL-LABEL: tst_select_i1_i1:
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; M2: andi $[[T0:[0-9]+]], $4, 1
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; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2: nop
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; M2: move $5, $6
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; M2: $[[BB0]]:
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; M2: jr $ra
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; M2: move $2, $5
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; CMOV: andi $[[T0:[0-9]+]], $4, 1
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; CMOV: movn $6, $5, $[[T0]]
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; CMOV: move $2, $6
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; SEL: andi $[[T0:[0-9]+]], $4, 1
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; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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; SEL: or $2, $[[T2]], $[[T1]]
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%r = select i1 %s, i1 %x, i1 %y
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ret i1 %r
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}
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define signext i8 @tst_select_i1_i8(i1 signext %s,
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i8 signext %x, i8 signext %y) {
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entry:
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; ALL-LABEL: tst_select_i1_i8:
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; M2: andi $[[T0:[0-9]+]], $4, 1
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; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2: nop
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; M2: move $5, $6
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; M2: $[[BB0]]:
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; M2: jr $ra
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; M2: move $2, $5
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; CMOV: andi $[[T0:[0-9]+]], $4, 1
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; CMOV: movn $6, $5, $[[T0]]
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; CMOV: move $2, $6
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; SEL: andi $[[T0:[0-9]+]], $4, 1
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; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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; SEL: or $2, $[[T2]], $[[T1]]
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%r = select i1 %s, i8 %x, i8 %y
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ret i8 %r
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}
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define signext i32 @tst_select_i1_i32(i1 signext %s,
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i32 signext %x, i32 signext %y) {
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entry:
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; ALL-LABEL: tst_select_i1_i32:
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; M2: andi $[[T0:[0-9]+]], $4, 1
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; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2: nop
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; M2: move $5, $6
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; M2: $[[BB0]]:
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; M2: jr $ra
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; M2: move $2, $5
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; CMOV: andi $[[T0:[0-9]+]], $4, 1
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; CMOV: movn $6, $5, $[[T0]]
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; CMOV: move $2, $6
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; SEL: andi $[[T0:[0-9]+]], $4, 1
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; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
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; SEL: or $2, $[[T2]], $[[T1]]
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%r = select i1 %s, i32 %x, i32 %y
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ret i32 %r
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}
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define signext i64 @tst_select_i1_i64(i1 signext %s,
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i64 signext %x, i64 signext %y) {
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entry:
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; ALL-LABEL: tst_select_i1_i64:
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; M2: andi $[[T0:[0-9]+]], $4, 1
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; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2: nop
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; M2: lw $[[T1:[0-9]+]], 16($sp)
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; M2: $[[BB0]]:
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; FIXME: This branch is redundant
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; M2: bnez $[[T0]], $[[BB1:BB[0-9_]+]]
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; M2: nop
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; M2: lw $[[T2:[0-9]+]], 20($sp)
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; M2: $[[BB1]]:
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; M2: move $2, $[[T1]]
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; M2: jr $ra
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; M2: move $3, $[[T2]]
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; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
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; CMOV-32: lw $2, 16($sp)
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; CMOV-32: movn $2, $6, $[[T0]]
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; CMOV-32: lw $3, 20($sp)
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; CMOV-32: movn $3, $7, $[[T0]]
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; SEL-32: andi $[[T0:[0-9]+]], $4, 1
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; SEL-32: selnez $[[T1:[0-9]+]], $6, $[[T0]]
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; SEL-32: lw $[[T2:[0-9]+]], 16($sp)
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; SEL-32: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]]
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; SEL-32: or $2, $[[T1]], $[[T3]]
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; SEL-32: selnez $[[T4:[0-9]+]], $7, $[[T0]]
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; SEL-32: lw $[[T5:[0-9]+]], 20($sp)
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; SEL-32: seleqz $[[T6:[0-9]+]], $[[T5]], $[[T0]]
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; SEL-32: or $3, $[[T4]], $[[T6]]
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; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
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; CMOV-64: movn $6, $5, $[[T0]]
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; CMOV-64: move $2, $6
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; SEL-64: andi $[[T0:[0-9]+]], $4, 1
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; FIXME: This shift is redundant
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; SEL-64: sll $[[T0]], $[[T0]], 0
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; SEL-64: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
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; SEL-64: selnez $[[T0]], $5, $[[T0]]
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; SEL-64: or $2, $[[T0]], $[[T1]]
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%r = select i1 %s, i64 %x, i64 %y
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ret i64 %r
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}
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define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {
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entry:
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; ALL-LABEL: tst_select_i1_float:
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; M2: andi $[[T0:[0-9]+]], $4, 1
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; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2: nop
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; M2: jr $ra
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; M2: mtc1 $6, $f0
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; M2: $[[BB0]]:
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; M2: jr $ra
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; M2: mtc1 $5, $f0
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; CMOV-32: mtc1 $6, $f0
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; CMOV-32: mtc1 $5, $f1
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; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
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; CMOV-32: movn.s $f0, $f1, $[[T0]]
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; SEL-32: mtc1 $5, $[[F0:f[0-9]+]]
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; SEL-32: mtc1 $6, $[[F1:f[0-9]+]]
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; SEL-32: mtc1 $4, $f0
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; SEL-32: sel.s $f0, $[[F1]], $[[F0]]
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; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
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; CMOV-64: movn.s $f14, $f13, $[[T0]]
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; CMOV-64: mov.s $f0, $f14
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; SEL-64: mtc1 $4, $f0
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; SEL-64: sel.s $f0, $f14, $f13
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%r = select i1 %s, float %x, float %y
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ret float %r
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}
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define float @tst_select_i1_float_reordered(float %x, float %y,
|
||||
i1 signext %s) {
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entry:
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; ALL-LABEL: tst_select_i1_float_reordered:
|
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; M2: andi $[[T0:[0-9]+]], $6, 1
|
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; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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; M2: nop
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; M2: mov.s $f12, $f14
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; M2: $[[BB0]]:
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; M2: jr $ra
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; M2: mov.s $f0, $f12
|
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|
||||
; CMOV-32: andi $[[T0:[0-9]+]], $6, 1
|
||||
; CMOV-32: movn.s $f14, $f12, $[[T0]]
|
||||
; CMOV-32: mov.s $f0, $f14
|
||||
|
||||
; SEL-32: mtc1 $6, $f0
|
||||
; SEL-32: sel.s $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: andi $[[T0:[0-9]+]], $6, 1
|
||||
; CMOV-64: movn.s $f13, $f12, $[[T0]]
|
||||
; CMOV-64: mov.s $f0, $f13
|
||||
|
||||
; SEL-64: mtc1 $6, $f0
|
||||
; SEL-64: sel.s $f0, $f13, $f12
|
||||
%r = select i1 %s, float %x, float %y
|
||||
ret float %r
|
||||
}
|
||||
|
||||
define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_i1_double:
|
||||
|
||||
; M2: andi $[[T0:[0-9]+]], $4, 1
|
||||
; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M2: ldc1 $f0, 16($sp)
|
||||
; M2: jr $ra
|
||||
; M2: nop
|
||||
; M2: $[[BB0]]:
|
||||
; M2: mtc1 $7, $f0
|
||||
; M2: jr $ra
|
||||
; M2: mtc1 $6, $f1
|
||||
|
||||
; CMOV-32: mtc1 $7, $[[F0:f[0-9]+]]
|
||||
; CMOV-32R1: mtc1 $6, $f{{[0-9]+}}
|
||||
; CMOV-32R2 mthc1 $6, $[[F0]]
|
||||
; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
|
||||
; CMOV-32: ldc1 $f0, 16($sp)
|
||||
; CMOV-32: movn.d $f0, $[[F0]], $[[T0]]
|
||||
|
||||
; SEL-32: mtc1 $7, $[[F0:f[0-9]+]]
|
||||
; SEL-32: mthc1 $6, $[[F0]]
|
||||
; SEL-32: ldc1 $[[F1:f[0-9]+]], 16($sp)
|
||||
; SEL-32: mtc1 $4, $f0
|
||||
; SEL-32: sel.d $f0, $[[F1]], $[[F0]]
|
||||
|
||||
; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
|
||||
; CMOV-64: movn.d $f14, $f13, $[[T0]]
|
||||
; CMOV-64: mov.d $f0, $f14
|
||||
|
||||
; SEL-64: mtc1 $4, $f0
|
||||
; SEL-64: sel.d $f0, $f14, $f13
|
||||
%r = select i1 %s, double %x, double %y
|
||||
ret double %r
|
||||
}
|
||||
|
||||
define double @tst_select_i1_double_reordered(double %x, double %y,
|
||||
i1 signext %s) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_i1_double_reordered:
|
||||
|
||||
; M2: lw $[[T0:[0-9]+]], 16($sp)
|
||||
; M2: andi $[[T1:[0-9]+]], $[[T0]], 1
|
||||
; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M2: mov.d $f12, $f14
|
||||
; M2: $[[BB0]]:
|
||||
; M2: jr $ra
|
||||
; M2: mov.d $f0, $f12
|
||||
|
||||
; CMOV-32: lw $[[T0:[0-9]+]], 16($sp)
|
||||
; CMOV-32: andi $[[T1:[0-9]+]], $[[T0]], 1
|
||||
; CMOV-32: movn.d $f14, $f12, $[[T1]]
|
||||
; CMOV-32: mov.d $f0, $f14
|
||||
|
||||
; SEL-32: lw $[[T0:[0-9]+]], 16($sp)
|
||||
; SEL-32: mtc1 $[[T0]], $f0
|
||||
; SEL-32: sel.d $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: andi $[[T0:[0-9]+]], $6, 1
|
||||
; CMOV-64: movn.d $f13, $f12, $[[T0]]
|
||||
; CMOV-64: mov.d $f0, $f13
|
||||
|
||||
; SEL-64: mtc1 $6, $f0
|
||||
; SEL-64: sel.d $f0, $f13, $f12
|
||||
%r = select i1 %s, double %x, double %y
|
||||
ret double %r
|
||||
}
|
||||
|
||||
define float @tst_select_fcmp_olt_float(float %x, float %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_olt_float:
|
||||
|
||||
; M2: c.olt.s $f12, $f14
|
||||
; M2: bc1t $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M2: mov.s $f12, $f14
|
||||
; M2: $[[BB0]]:
|
||||
; M2: jr $ra
|
||||
; M2: mov.s $f0, $f12
|
||||
|
||||
; CMOV-32: c.olt.s $f12, $f14
|
||||
; CMOV-32: movt.s $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.s $f0, $f14
|
||||
|
||||
; SEL-32: cmp.lt.s $f0, $f12, $f14
|
||||
; SEL-32: sel.s $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.olt.s $f12, $f13
|
||||
; CMOV-64: movt.s $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.s $f0, $f13
|
||||
|
||||
; SEL-64: cmp.lt.s $f0, $f12, $f13
|
||||
; SEL-64: sel.s $f0, $f13, $f12
|
||||
%s = fcmp olt float %x, %y
|
||||
%r = select i1 %s, float %x, float %y
|
||||
ret float %r
|
||||
}
|
||||
|
||||
define float @tst_select_fcmp_ole_float(float %x, float %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_ole_float:
|
||||
|
||||
; M2: c.ole.s $f12, $f14
|
||||
; M2: bc1t $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M2: mov.s $f12, $f14
|
||||
; M2: $[[BB0]]:
|
||||
; M2: jr $ra
|
||||
; M2: mov.s $f0, $f12
|
||||
|
||||
; CMOV-32: c.ole.s $f12, $f14
|
||||
; CMOV-32: movt.s $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.s $f0, $f14
|
||||
|
||||
; SEL-32: cmp.le.s $f0, $f12, $f14
|
||||
; SEL-32: sel.s $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.ole.s $f12, $f13
|
||||
; CMOV-64: movt.s $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.s $f0, $f13
|
||||
|
||||
; SEL-64: cmp.le.s $f0, $f12, $f13
|
||||
; SEL-64: sel.s $f0, $f13, $f12
|
||||
%s = fcmp ole float %x, %y
|
||||
%r = select i1 %s, float %x, float %y
|
||||
ret float %r
|
||||
}
|
||||
|
||||
define float @tst_select_fcmp_ogt_float(float %x, float %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_ogt_float:
|
||||
|
||||
; M2: c.ule.s $f12, $f14
|
||||
; M2: bc1f $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M2: mov.s $f12, $f14
|
||||
; M2: $[[BB0]]:
|
||||
; M2: jr $ra
|
||||
; M2: mov.s $f0, $f12
|
||||
|
||||
; CMOV-32: c.ule.s $f12, $f14
|
||||
; CMOV-32: movf.s $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.s $f0, $f14
|
||||
|
||||
; SEL-32: cmp.lt.s $f0, $f14, $f12
|
||||
; SEL-32: sel.s $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.ule.s $f12, $f13
|
||||
; CMOV-64: movf.s $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.s $f0, $f13
|
||||
|
||||
; SEL-64: cmp.lt.s $f0, $f13, $f12
|
||||
; SEL-64: sel.s $f0, $f13, $f12
|
||||
%s = fcmp ogt float %x, %y
|
||||
%r = select i1 %s, float %x, float %y
|
||||
ret float %r
|
||||
}
|
||||
|
||||
define float @tst_select_fcmp_oge_float(float %x, float %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_oge_float:
|
||||
|
||||
; M2: c.ult.s $f12, $f14
|
||||
; M2: bc1f $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M2: mov.s $f12, $f14
|
||||
; M2: $[[BB0]]:
|
||||
; M2: jr $ra
|
||||
; M2: mov.s $f0, $f12
|
||||
|
||||
; CMOV-32: c.ult.s $f12, $f14
|
||||
; CMOV-32: movf.s $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.s $f0, $f14
|
||||
|
||||
; SEL-32: cmp.le.s $f0, $f14, $f12
|
||||
; SEL-32: sel.s $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.ult.s $f12, $f13
|
||||
; CMOV-64: movf.s $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.s $f0, $f13
|
||||
|
||||
; SEL-64: cmp.le.s $f0, $f13, $f12
|
||||
; SEL-64: sel.s $f0, $f13, $f12
|
||||
%s = fcmp oge float %x, %y
|
||||
%r = select i1 %s, float %x, float %y
|
||||
ret float %r
|
||||
}
|
||||
|
||||
define float @tst_select_fcmp_oeq_float(float %x, float %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_oeq_float:
|
||||
|
||||
; M2: c.eq.s $f12, $f14
|
||||
; M2: bc1t $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M2: mov.s $f12, $f14
|
||||
; M2: $[[BB0]]:
|
||||
; M2: jr $ra
|
||||
; M2: mov.s $f0, $f12
|
||||
|
||||
; CMOV-32: c.eq.s $f12, $f14
|
||||
; CMOV-32: movt.s $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.s $f0, $f14
|
||||
|
||||
; SEL-32: cmp.eq.s $f0, $f12, $f14
|
||||
; SEL-32: sel.s $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.eq.s $f12, $f13
|
||||
; CMOV-64: movt.s $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.s $f0, $f13
|
||||
|
||||
; SEL-64: cmp.eq.s $f0, $f12, $f13
|
||||
; SEL-64: sel.s $f0, $f13, $f12
|
||||
%s = fcmp oeq float %x, %y
|
||||
%r = select i1 %s, float %x, float %y
|
||||
ret float %r
|
||||
}
|
||||
|
||||
define float @tst_select_fcmp_one_float(float %x, float %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_one_float:
|
||||
|
||||
; M2: c.ueq.s $f12, $f14
|
||||
; M2: bc1f $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M2: mov.s $f12, $f14
|
||||
; M2: $[[BB0]]:
|
||||
; M2: jr $ra
|
||||
; M2: mov.s $f0, $f12
|
||||
|
||||
; CMOV-32: c.ueq.s $f12, $f14
|
||||
; CMOV-32: movf.s $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.s $f0, $f14
|
||||
|
||||
; SEL-32: cmp.ueq.s $f0, $f12, $f14
|
||||
; SEL-32: mfc1 $[[T0:[0-9]+]], $f0
|
||||
; SEL-32: not $[[T0]], $[[T0]]
|
||||
; SEL-32: mtc1 $[[T0:[0-9]+]], $f0
|
||||
; SEL-32: sel.s $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.ueq.s $f12, $f13
|
||||
; CMOV-64: movf.s $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.s $f0, $f13
|
||||
|
||||
; SEL-64: cmp.ueq.s $f0, $f12, $f13
|
||||
; SEL-64: mfc1 $[[T0:[0-9]+]], $f0
|
||||
; SEL-64: not $[[T0]], $[[T0]]
|
||||
; SEL-64: mtc1 $[[T0:[0-9]+]], $f0
|
||||
; SEL-64: sel.s $f0, $f13, $f12
|
||||
|
||||
%s = fcmp one float %x, %y
|
||||
%r = select i1 %s, float %x, float %y
|
||||
ret float %r
|
||||
}
|
||||
|
||||
define double @tst_select_fcmp_olt_double(double %x, double %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_olt_double:
|
||||
|
||||
; M2: c.olt.d $f12, $f14
|
||||
; M2: bc1t $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M2: mov.d $f12, $f14
|
||||
; M2: $[[BB0]]:
|
||||
; M2: jr $ra
|
||||
; M2: mov.d $f0, $f12
|
||||
|
||||
; CMOV-32: c.olt.d $f12, $f14
|
||||
; CMOV-32: movt.d $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.d $f0, $f14
|
||||
|
||||
; SEL-32: cmp.lt.d $f0, $f12, $f14
|
||||
; SEL-32: sel.d $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.olt.d $f12, $f13
|
||||
; CMOV-64: movt.d $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.d $f0, $f13
|
||||
|
||||
; SEL-64: cmp.lt.d $f0, $f12, $f13
|
||||
; SEL-64: sel.d $f0, $f13, $f12
|
||||
%s = fcmp olt double %x, %y
|
||||
%r = select i1 %s, double %x, double %y
|
||||
ret double %r
|
||||
}
|
||||
|
||||
define double @tst_select_fcmp_ole_double(double %x, double %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_ole_double:
|
||||
|
||||
; M2: c.ole.d $f12, $f14
|
||||
; M2: bc1t $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M2: mov.d $f12, $f14
|
||||
; M2: $[[BB0]]:
|
||||
; M2: jr $ra
|
||||
; M2: mov.d $f0, $f12
|
||||
|
||||
; CMOV-32: c.ole.d $f12, $f14
|
||||
; CMOV-32: movt.d $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.d $f0, $f14
|
||||
|
||||
; SEL-32: cmp.le.d $f0, $f12, $f14
|
||||
; SEL-32: sel.d $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.ole.d $f12, $f13
|
||||
; CMOV-64: movt.d $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.d $f0, $f13
|
||||
|
||||
; SEL-64: cmp.le.d $f0, $f12, $f13
|
||||
; SEL-64: sel.d $f0, $f13, $f12
|
||||
%s = fcmp ole double %x, %y
|
||||
%r = select i1 %s, double %x, double %y
|
||||
ret double %r
|
||||
}
|
||||
|
||||
define double @tst_select_fcmp_ogt_double(double %x, double %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_ogt_double:
|
||||
|
||||
; M2: c.ule.d $f12, $f14
|
||||
; M2: bc1f $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M2: mov.d $f12, $f14
|
||||
; M2: $[[BB0]]:
|
||||
; M2: jr $ra
|
||||
; M2: mov.d $f0, $f12
|
||||
|
||||
; CMOV-32: c.ule.d $f12, $f14
|
||||
; CMOV-32: movf.d $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.d $f0, $f14
|
||||
|
||||
; SEL-32: cmp.lt.d $f0, $f14, $f12
|
||||
; SEL-32: sel.d $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.ule.d $f12, $f13
|
||||
; CMOV-64: movf.d $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.d $f0, $f13
|
||||
|
||||
; SEL-64: cmp.lt.d $f0, $f13, $f12
|
||||
; SEL-64: sel.d $f0, $f13, $f12
|
||||
%s = fcmp ogt double %x, %y
|
||||
%r = select i1 %s, double %x, double %y
|
||||
ret double %r
|
||||
}
|
||||
|
||||
define double @tst_select_fcmp_oge_double(double %x, double %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_oge_double:
|
||||
|
||||
; M2: c.ult.d $f12, $f14
|
||||
; M2: bc1f $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M2: mov.d $f12, $f14
|
||||
; M2: $[[BB0]]:
|
||||
; M2: jr $ra
|
||||
; M2: mov.d $f0, $f12
|
||||
|
||||
; CMOV-32: c.ult.d $f12, $f14
|
||||
; CMOV-32: movf.d $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.d $f0, $f14
|
||||
|
||||
; SEL-32: cmp.le.d $f0, $f14, $f12
|
||||
; SEL-32: sel.d $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.ult.d $f12, $f13
|
||||
; CMOV-64: movf.d $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.d $f0, $f13
|
||||
|
||||
; SEL-64: cmp.le.d $f0, $f13, $f12
|
||||
; SEL-64: sel.d $f0, $f13, $f12
|
||||
%s = fcmp oge double %x, %y
|
||||
%r = select i1 %s, double %x, double %y
|
||||
ret double %r
|
||||
}
|
||||
|
||||
define double @tst_select_fcmp_oeq_double(double %x, double %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_oeq_double:
|
||||
|
||||
; M2: c.eq.d $f12, $f14
|
||||
; M2: bc1t $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M2: mov.d $f12, $f14
|
||||
; M2: $[[BB0]]:
|
||||
; M2: jr $ra
|
||||
; M2: mov.d $f0, $f12
|
||||
|
||||
; CMOV-32: c.eq.d $f12, $f14
|
||||
; CMOV-32: movt.d $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.d $f0, $f14
|
||||
|
||||
; SEL-32: cmp.eq.d $f0, $f12, $f14
|
||||
; SEL-32: sel.d $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.eq.d $f12, $f13
|
||||
; CMOV-64: movt.d $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.d $f0, $f13
|
||||
|
||||
; SEL-64: cmp.eq.d $f0, $f12, $f13
|
||||
; SEL-64: sel.d $f0, $f13, $f12
|
||||
%s = fcmp oeq double %x, %y
|
||||
%r = select i1 %s, double %x, double %y
|
||||
ret double %r
|
||||
}
|
||||
|
||||
define double @tst_select_fcmp_one_double(double %x, double %y) {
|
||||
entry:
|
||||
; ALL-LABEL: tst_select_fcmp_one_double:
|
||||
|
||||
; M2: c.ueq.d $f12, $f14
|
||||
; M2: bc1f $[[BB0:BB[0-9_]+]]
|
||||
; M2: nop
|
||||
; M2: mov.d $f12, $f14
|
||||
; M2: $[[BB0]]:
|
||||
; M2: jr $ra
|
||||
; M2: mov.d $f0, $f12
|
||||
|
||||
; CMOV-32: c.ueq.d $f12, $f14
|
||||
; CMOV-32: movf.d $f14, $f12, $fcc0
|
||||
; CMOV-32: mov.d $f0, $f14
|
||||
|
||||
; SEL-32: cmp.ueq.d $f0, $f12, $f14
|
||||
; SEL-32: mfc1 $[[T0:[0-9]+]], $f0
|
||||
; SEL-32: not $[[T0]], $[[T0]]
|
||||
; SEL-32: mtc1 $[[T0:[0-9]+]], $f0
|
||||
; SEL-32: sel.d $f0, $f14, $f12
|
||||
|
||||
; CMOV-64: c.ueq.d $f12, $f13
|
||||
; CMOV-64: movf.d $f13, $f12, $fcc0
|
||||
; CMOV-64: mov.d $f0, $f13
|
||||
|
||||
; SEL-64: cmp.ueq.d $f0, $f12, $f13
|
||||
; SEL-64: mfc1 $[[T0:[0-9]+]], $f0
|
||||
; SEL-64: not $[[T0]], $[[T0]]
|
||||
; SEL-64: mtc1 $[[T0:[0-9]+]], $f0
|
||||
; SEL-64: sel.d $f0, $f13, $f12
|
||||
%s = fcmp one double %x, %y
|
||||
%r = select i1 %s, double %x, double %y
|
||||
ret double %r
|
||||
}
|
||||
Reference in New Issue
Block a user