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Add <imp-def> operands when reloading into physregs.
When an instruction only writes sub-registers, it is still necessary to add an <imp-def> operand for the super-register. When reloading into a virtual register, rewriting will add the operand, but when loading directly into a virtual register, the <imp-def> operand is still necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152095 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -935,6 +935,8 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
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if (TargetRegisterInfo::isPhysicalRegister(DestReg))
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MIB.addReg(DestReg, RegState::ImplicitDefine);
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}
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}
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} else
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} else
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llvm_unreachable("Unknown reg class!");
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llvm_unreachable("Unknown reg class!");
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@ -953,6 +955,8 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
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if (TargetRegisterInfo::isPhysicalRegister(DestReg))
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MIB.addReg(DestReg, RegState::ImplicitDefine);
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} else
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} else
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llvm_unreachable("Unknown reg class!");
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llvm_unreachable("Unknown reg class!");
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break;
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break;
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@ -1,4 +1,5 @@
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; RUN: llc < %s -verify-machineinstrs
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; RUN: llc < %s -verify-machineinstrs
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; RUN: llc < %s -verify-machineinstrs -O0
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; PR12177
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; PR12177
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;
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;
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; This test case spills a QQQQ register.
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; This test case spills a QQQQ register.
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