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Add, sub and shuffle are legal for all vector types

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27305 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-03-31 19:48:58 +00:00
parent b067a1e7e6
commit 32a988a095
1 changed files with 9 additions and 8 deletions
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17
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -171,12 +171,16 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
// First set operation action for all vector types to expand. Then we // First set operation action for all vector types to expand. Then we
// will selectively turn on ones that can be effectively codegen'd. // will selectively turn on ones that can be effectively codegen'd.
for (unsigned VT = (unsigned)MVT::Vector + 1; for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
VT != (unsigned)MVT::LAST_VALUETYPE; VT++) { VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand); // Add and sub are legal for all supported VT's.
setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand); setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Legal);
setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand); setOperationAction(ISD::DIV , (MVT::ValueType)VT, Expand);
setOperationAction(ISD::REM , (MVT::ValueType)VT, Expand);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
@ -188,10 +192,7 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
setOperationAction(ISD::ADD , MVT::v4f32, Legal);
setOperationAction(ISD::SUB , MVT::v4f32, Legal);
setOperationAction(ISD::MUL , MVT::v4f32, Legal); setOperationAction(ISD::MUL , MVT::v4f32, Legal);
setOperationAction(ISD::ADD , MVT::v4i32, Legal);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);