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Reorganize these slightly according to operand type.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132128 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2011-05-26 18:22:26 +00:00
parent 78e72d60ec
commit 32bfb2c513
1 changed files with 2 additions and 2 deletions
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4
lib/Target/ARM/ARMAsmPrinter.cpp
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@ -426,13 +426,12 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
return true;
O << (MI->getOperand(OpNum).getImm() & 0xffff);
return false;
case 'M': // A register range suitable for LDM/STM.
case 'p': // The high single-precision register of a VFP double-precision
// register.
case 'e': // The low doubleword register of a NEON quad register.
case 'f': // The high doubleword register of a NEON quad register.
case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
case 'A': // A memory operand for a VLD1/VST1 instruction.
case 'M': // A register range suitable for LDM/STM.
case 'Q': // The least significant register of a pair.
case 'R': // The most significant register of a pair.
case 'H': // The highest-numbered register of a pair.
@ -454,6 +453,7 @@ bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
if (ExtraCode[1] != 0) return true; // Unknown modifier.
switch (ExtraCode[0]) {
case 'A': // A memory operand for a VLD1/VST1 instruction.
default: return true; // Unknown modifier.
case 'm': // The base register of a memory operand.
if (!MI->getOperand(OpNum).isReg())