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Add bad register checks for Thumb2 Ld/St instructions.

Browse Source 
rdar://problem/9269047


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129387 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-04-12 21:17:51 +00:00
parent c558bf3972
commit 32cefad4b3
2 changed files with 55 additions and 0 deletions
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45
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
View File

@ -1862,6 +1862,47 @@ static bool DisassembleThumb2PreLoad(MCInst &MI, unsigned Opcode, uint32_t insn,
return true; return true;
} }
static bool BadRegsThumb2LdSt(unsigned Opcode, uint32_t insn, bool Load,
unsigned R0, unsigned R1, unsigned R2, bool UseRm, bool WB) {
// Inst{22-21} encodes the data item transferred for load/store.
// For single word, it is encoded as ob10.
bool Word = (slice(insn, 22, 21) == 2);
if (UseRm && BadReg(R2)) {
DEBUG(errs() << "if BadReg(m) then UNPREDICTABLE\n");
return true;
}
if (Load) {
if (!Word && R0 == 13) {
DEBUG(errs() << "if t == 13 then UNPREDICTABLE\n");
return true;
}
} else {
if (WB && R0 == R1) {
DEBUG(errs() << "if wback && n == t then UNPREDICTABLE\n");
return true;
}
if ((WB && R0 == 15) || (!WB && R1 == 15)) {
DEBUG(errs() << "if Rn == '1111' then UNDEFINED\n");
return true;
}
if (Word) {
if ((WB && R1 == 15) || (!WB && R0 == 15)) {
DEBUG(errs() << "if t == 15 then UNPREDICTABLE\n");
return true;
}
} else {
if ((WB && BadReg(R1)) || (!WB && BadReg(R0))) {
DEBUG(errs() << "if BadReg(t) then UNPREDICTABLE\n");
return true;
}
}
}
return false;
}
// A6.3.10 Store single data item // A6.3.10 Store single data item
// A6.3.9 Load byte, memory hints // A6.3.9 Load byte, memory hints
// A6.3.8 Load halfword, memory hints // A6.3.8 Load halfword, memory hints
@ -1961,6 +2002,10 @@ static bool DisassembleThumb2LdSt(bool Load, MCInst &MI, unsigned Opcode,
++OpIdx; ++OpIdx;
} }
if (BadRegsThumb2LdSt(Opcode, insn, Load, R0, R1, R2, ThreeReg & !TIED_TO,
TIED_TO))
return false;
assert(OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() assert(OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate()
&& !OpInfo[OpIdx].isOptionalDef() && !OpInfo[OpIdx].isOptionalDef()
&& "Pure imm operand expected"); && "Pure imm operand expected");

10
test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt Normal file
View File

@ -0,0 +1,10 @@
# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1|
# -------------------------------------------------------------------------------------------------
#
# if Rn == '1111' then UNDEFINED
0x4f 0xf8 0xff 0xeb