From 32f3d08cdebd8941f2149a8f32acd45bd224ca8d Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sun, 17 Nov 2002 21:56:10 +0000 Subject: [PATCH] Convert to use an enum to access def/use/use&def information. These make reading code much easier than just seeing "true, false" especially when default parameters default one but not both arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4717 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineInstr.h | 56 +++++++++++++++++----- include/llvm/CodeGen/MachineInstrBuilder.h | 20 ++++---- 2 files changed, 54 insertions(+), 22 deletions(-) diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h index 79556010807..499ec2498cf 100644 --- a/include/llvm/CodeGen/MachineInstr.h +++ b/include/llvm/CodeGen/MachineInstr.h @@ -20,6 +20,20 @@ class TargetMachine; typedef int MachineOpCode; +/// MOTy - MachineOperandType - This namespace contains an enum that describes +/// how the machine operand is used by the instruction: is it read, defined, or +/// both? Note that the MachineInstr/Operator class currently uses bool +/// arguments to represent this information instead of an enum. Eventually this +/// should change over to use this _easier to read_ representation instead. +/// +namespace MOTy { + enum UseType { + Use, /// This machine operand is only read by the instruction + Def, /// This machine operand is only written by the instruction + UseAndDef /// This machine operand is read AND written + }; +} + //--------------------------------------------------------------------------- // class MachineOperand // @@ -102,18 +116,26 @@ private: flags(0), regNum(-1) {} - MachineOperand(int Reg, MachineOperandType OpTy, bool isDef = false) + MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy) : immedVal(0), opType(OpTy), - flags(isDef ? DEFFLAG : 0), - regNum(Reg) {} + regNum(Reg) { + switch (UseTy) { + case MOTy::Use: flags = 0; break; + case MOTy::Def: flags = DEFFLAG; break; + case MOTy::UseAndDef: flags = DEFUSEFLAG; break; + default: assert(0 && "Invalid value for UseTy!"); + } + } - MachineOperand(Value *V, MachineOperandType OpTy, - bool isDef = false, bool isDNU = false) - : value(V), - opType(OpTy), - regNum(-1) { - flags = (isDef ? DEFFLAG : 0) | (isDNU ? DEFUSEFLAG : 0); + MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy) + : value(V), opType(OpTy), regNum(-1) { + switch (UseTy) { + case MOTy::Use: flags = 0; break; + case MOTy::Def: flags = DEFFLAG; break; + case MOTy::UseAndDef: flags = DEFUSEFLAG; break; + default: assert(0 && "Invalid value for UseTy!"); + } } public: @@ -367,7 +389,14 @@ public: assert(!OperandsComplete() && "Trying to add an operand to a machine instr that is already done!"); operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister, - isDef, isDefAndUse)); + !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def))); + } + + void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) { + assert(!OperandsComplete() && + "Trying to add an operand to a machine instr that is already done!"); + operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister, + UTy)); } /// addRegOperand - Add a symbolic virtual register reference... @@ -376,7 +405,7 @@ public: assert(!OperandsComplete() && "Trying to add an operand to a machine instr that is already done!"); operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister, - isDef)); + isDef ? MOTy::Def : MOTy::Use)); } /// addPCDispOperand - Add a PC relative displacement operand to the MI @@ -384,7 +413,8 @@ public: void addPCDispOperand(Value *V) { assert(!OperandsComplete() && "Trying to add an operand to a machine instr that is already done!"); - operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp)); + operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp, + MOTy::Use)); } /// addMachineRegOperand - Add a virtual register operand to this MachineInstr @@ -393,7 +423,7 @@ public: assert(!OperandsComplete() && "Trying to add an operand to a machine instr that is already done!"); operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister, - isDef)); + isDef ? MOTy::Def : MOTy::Use)); insertUsedReg(reg); } diff --git a/include/llvm/CodeGen/MachineInstrBuilder.h b/include/llvm/CodeGen/MachineInstrBuilder.h index c8ff18fdb2e..1d8edbe171a 100644 --- a/include/llvm/CodeGen/MachineInstrBuilder.h +++ b/include/llvm/CodeGen/MachineInstrBuilder.h @@ -18,7 +18,7 @@ #include "llvm/CodeGen/MachineInstr.h" -struct MachineInstrBuilder { +struct MachineInstrBuilder { MachineInstr *MI; MachineInstrBuilder(MachineInstr *mi) : MI(mi) {} @@ -29,16 +29,17 @@ struct MachineInstrBuilder { /// addReg - Add a new virtual register operand... /// - const MachineInstrBuilder &addReg(int RegNo, bool isDef = false) const { - MI->addRegOperand(RegNo, isDef); + const MachineInstrBuilder &addReg(int RegNo, + MOTy::UseType Ty = MOTy::Use) const { + MI->addRegOperand(RegNo, Ty); return *this; } /// addReg - Add an LLVM value that is to be used as a register... /// - const MachineInstrBuilder &addReg(Value *V, bool isDef = false, - bool isDNU = false) const { - MI->addRegOperand(V, isDef, isDNU); + const MachineInstrBuilder &addReg(Value *V, + MOTy::UseType Ty = MOTy::Use) const { + MI->addRegOperand(V, Ty); return *this; } @@ -61,8 +62,9 @@ struct MachineInstrBuilder { /// addMReg - Add a machine register operand... /// - const MachineInstrBuilder &addMReg(int Reg, bool isDef = false) const { - MI->addMachineRegOperand(Reg, isDef); + const MachineInstrBuilder &addMReg(int Reg, + MOTy::UseType Ty = MOTy::Use) const { + MI->addMachineRegOperand(Reg, Ty); return *this; } @@ -106,7 +108,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, MachineOpCode Opcode, unsigned NumOperands, unsigned DestReg) { return MachineInstrBuilder(new MachineInstr(BB, Opcode, NumOperands+1)).addReg(DestReg, - true); + MOTy::Def); } #endif