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Add emitAssemblyMethod to TargetMachine

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@635 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2001-09-19 13:47:12 +00:00
parent 80acc6cf43
commit 32f600a8bf
1 changed files with 11 additions and 9 deletions
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20
lib/Target/SparcV9/SparcV9Internals.h
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@@ -441,7 +441,7 @@ const MachineInstrDescriptor SparcMachineInstrDesc[] = {
// numDelaySlots (in cycles) // numDelaySlots (in cycles)
// latency (in cycles) // latency (in cycles)
// instr sched class (defined above) // instr sched class (defined above)
// instr class flags (defined in TargretMachine.h) // instr class flags (defined in MachineInstrInfo.h)
{ "NOP", 0, -1, 0, false, 0, 1, SPARC_NONE, M_NOP_FLAG }, { "NOP", 0, -1, 0, false, 0, 1, SPARC_NONE, M_NOP_FLAG },
@@ -900,8 +900,6 @@ class UltraSparcRegInfo : public MachineRegInfo
MachineInstr * getCopy2RegMI(const Value *SrcVal, const unsigned Reg, MachineInstr * getCopy2RegMI(const Value *SrcVal, const unsigned Reg,
unsigned RegClassID) const ; unsigned RegClassID) const ;
public: public:
@@ -996,7 +994,6 @@ class UltraSparcRegInfo : public MachineRegInfo
// given the unified register number, this gives the name // given the unified register number, this gives the name
inline const string getUnifiedRegName(int reg) const { inline const string getUnifiedRegName(int reg) const {
if( reg < 32 ) if( reg < 32 )
return SparcIntRegOrder::getRegName(reg); return SparcIntRegOrder::getRegName(reg);
else if ( reg < (64 + 32) ) else if ( reg < (64 + 32) )
@@ -1728,16 +1725,21 @@ public:
UltraSparc(); UltraSparc();
virtual ~UltraSparc() {} virtual ~UltraSparc() {}
virtual const MachineInstrInfo& getInstrInfo() const { return instrInfo; } virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
virtual const MachineSchedInfo& getSchedInfo() const { return schedInfo; } virtual const MachineRegInfo &getRegInfo() const { return regInfo; }
virtual const MachineRegInfo& getRegInfo() const { return regInfo; }
// compileMethod - For the sparc, we do instruction selection, followed by // compileMethod - For the sparc, we do instruction selection, followed by
// delay slot scheduling, then register allocation. // delay slot scheduling, then register allocation.
// //
virtual bool compileMethod(Method *M); virtual bool compileMethod(Method *M);
//
// emitAssembly - Output assembly language code (a .s file) for the specified
// module. The specified module must have been compiled before this may be
// used.
//
virtual void emitAssembly(const Module *M, ostream &OutStr);
}; };