6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-11-01 00:17:01 +00:00
Code Issues Projects Releases Wiki Activity

Rename load/store instructions to include an RI suffix

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24784 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2005-12-17 20:18:49 +00:00
parent 84e2abf116
commit 331355cf7d
4 changed files with 102 additions and 108 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@@ -41,12 +41,10 @@ static const TargetRegisterClass *getClass(unsigned SrcReg) {
void SparcV8RegisterInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *rc) const {
const TargetRegisterClass *RC = getClass(SrcReg);
const TargetRegisterClass *RC) const {
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
if (RC == V8::IntRegsRegisterClass)
BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0)
BuildMI (MBB, I, V8::STri, 3).addFrameIndex (FrameIdx).addSImm (0)
.addReg (SrcReg);
else if (RC == V8::FPRegsRegisterClass)
BuildMI (MBB, I, V8::STFri, 3).addFrameIndex (FrameIdx).addSImm (0)
@@ -61,10 +59,9 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
void SparcV8RegisterInfo::
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *rc) const {
const TargetRegisterClass *RC = getClass(DestReg);
const TargetRegisterClass *RC) const {
if (RC == V8::IntRegsRegisterClass)
BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
BuildMI (MBB, I, V8::LDri, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
else if (RC == V8::FPRegsRegisterClass)
BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx)
.addSImm (0);