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Make the branch encoding for tBcc more obvious that it's a 4-byte opcode

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followed by a conditional and imm8.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132179 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2011-05-27 03:50:53 +00:00
parent 86bbcbf4b0
commit 33281b2361
2 changed files with 5 additions and 1 deletions
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4
lib/Target/ARM/ARMInstrFormats.td
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@ -1023,6 +1023,10 @@ class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
}
class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
class T1BranchCond<bits<4> opcode> : Encoding16 {
let Inst{15-12} = opcode;
}
// Helper classes to encode Thumb1 loads and stores. For immediates, the
// following bits are used for "opA" (see A6.2.4):
//

2
lib/Target/ARM/ARMInstrThumb.td
View File

@ -551,7 +551,7 @@ let isBranch = 1, isTerminator = 1 in
def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
"b${p}\t$target",
[/*(ARMbrcond bb:$target, imm:$cc)*/]>,
T1Encoding<{1,1,0,1,?,?}> {
T1BranchCond<{1,1,0,1}> {
bits<4> p;
bits<8> target;
let Inst{11-8} = p;