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https://github.com/c64scene-ar/llvm-6502.git
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Do some heroic rri address matching (shamelessly stolen from x86 backend). Not tested though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75929 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -52,6 +52,8 @@ namespace {
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const char* Modifier = 0);
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void printRIAddrOperand(const MachineInstr *MI, int OpNum,
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const char* Modifier = 0);
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void printRRIAddrOperand(const MachineInstr *MI, int OpNum,
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const char* Modifier = 0);
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bool printInstruction(const MachineInstr *MI); // autogenerated.
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void printMachineInstruction(const MachineInstr * MI);
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@@ -196,10 +198,31 @@ void SystemZAsmPrinter::printRIAddrOperand(const MachineInstr *MI, int OpNum,
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printOperand(MI, OpNum+1);
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// Print base operand (if any)
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if (!(Base.isReg() && Base.getReg() == SystemZ::R0D)) {
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if (Base.getReg()) {
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O << '(';
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printOperand(MI, OpNum);
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O << ')';
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}
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}
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void SystemZAsmPrinter::printRRIAddrOperand(const MachineInstr *MI, int OpNum,
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const char* Modifier) {
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const MachineOperand &Base = MI->getOperand(OpNum);
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const MachineOperand &Index = MI->getOperand(OpNum);
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// Print displacement operand.
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printOperand(MI, OpNum+2);
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// Print base operand (if any)
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if (Base.getReg()) {
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O << '(';
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printOperand(MI, OpNum);
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if (Index.getReg()) {
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O << ',';
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printOperand(MI, OpNum+1);
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}
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O << ')';
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} else
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assert(!Index.getReg() && "Should allocate base register first!");
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}
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