From 339ffedca9f5f367d26507eb631fd5f929c04677 Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Mon, 18 Feb 2008 17:55:26 +0000 Subject: [PATCH] Don't mark scalar integer multiplication as Expand on x86, since x86 has plain one-result scalar integer multiplication instructions. This avoids expanding such instructions into MUL_LOHI sequences that must be special-cased at isel time, and avoids the problem with that code that provented memory operands from being folded. This fixes PR1874, addressesing the most common case. The uncommon cases of optimizing multiply-high operations will require work in DAGCombiner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47277 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86ISelLowering.cpp | 11 ++++++----- test/CodeGen/X86/mul-remat.ll | 8 ++++++++ 2 files changed, 14 insertions(+), 5 deletions(-) create mode 100644 test/CodeGen/X86/mul-remat.ll diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 3e1f9428c91..54440162209 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -169,35 +169,31 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); } - // Scalar integer multiply, multiply-high, divide, and remainder are + // Scalar integer multiply-high, divide, and remainder are // lowered to use operations that produce two results, to match the // available instructions. This exposes the two-result form to trivial // CSE, which is able to combine x/y and x%y into a single instruction, // for example. The single-result multiply instructions are introduced // in X86ISelDAGToDAG.cpp, after CSE, for uses where the the high part // is not needed. - setOperationAction(ISD::MUL , MVT::i8 , Expand); setOperationAction(ISD::MULHS , MVT::i8 , Expand); setOperationAction(ISD::MULHU , MVT::i8 , Expand); setOperationAction(ISD::SDIV , MVT::i8 , Expand); setOperationAction(ISD::UDIV , MVT::i8 , Expand); setOperationAction(ISD::SREM , MVT::i8 , Expand); setOperationAction(ISD::UREM , MVT::i8 , Expand); - setOperationAction(ISD::MUL , MVT::i16 , Expand); setOperationAction(ISD::MULHS , MVT::i16 , Expand); setOperationAction(ISD::MULHU , MVT::i16 , Expand); setOperationAction(ISD::SDIV , MVT::i16 , Expand); setOperationAction(ISD::UDIV , MVT::i16 , Expand); setOperationAction(ISD::SREM , MVT::i16 , Expand); setOperationAction(ISD::UREM , MVT::i16 , Expand); - setOperationAction(ISD::MUL , MVT::i32 , Expand); setOperationAction(ISD::MULHS , MVT::i32 , Expand); setOperationAction(ISD::MULHU , MVT::i32 , Expand); setOperationAction(ISD::SDIV , MVT::i32 , Expand); setOperationAction(ISD::UDIV , MVT::i32 , Expand); setOperationAction(ISD::SREM , MVT::i32 , Expand); setOperationAction(ISD::UREM , MVT::i32 , Expand); - setOperationAction(ISD::MUL , MVT::i64 , Expand); setOperationAction(ISD::MULHS , MVT::i64 , Expand); setOperationAction(ISD::MULHU , MVT::i64 , Expand); setOperationAction(ISD::SDIV , MVT::i64 , Expand); @@ -205,6 +201,11 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) setOperationAction(ISD::SREM , MVT::i64 , Expand); setOperationAction(ISD::UREM , MVT::i64 , Expand); + // 8, 16, and 32-bit plain multiply are legal. And 64-bit multiply + // is also legal on x86-64. + if (!Subtarget->is64Bit()) + setOperationAction(ISD::MUL , MVT::i64 , Expand); + setOperationAction(ISD::BR_JT , MVT::Other, Expand); setOperationAction(ISD::BRCOND , MVT::Other, Custom); setOperationAction(ISD::BR_CC , MVT::Other, Expand); diff --git a/test/CodeGen/X86/mul-remat.ll b/test/CodeGen/X86/mul-remat.ll new file mode 100644 index 00000000000..ffc8cc0ba6b --- /dev/null +++ b/test/CodeGen/X86/mul-remat.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=x86 | grep mov | count 1 +; PR1874 + +define i32 @test(i32 %a, i32 %b) { +entry: + %tmp3 = mul i32 %b, %a + ret i32 %tmp3 +}