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Allow trailing physreg RegisterSDNode operands on non-variadic instructions.
Also allow trailing register mask operands on non-variadic both MachineSDNodes and MachineInstrs. The extra physreg RegisterSDNode operands are added to the MI as <imp-use> operands. This makes it possible to have non-variadic call instructions. Call and return instructions really are non-variadic, the argument registers should only be used implicitly - they are not part of the encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159727 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -660,7 +660,9 @@ void MachineInstr::addOperand(const MachineOperand &Op) {
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// OpNo now points as the desired insertion point. Unless this is a variadic
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// instruction, only implicit regs are allowed beyond MCID->getNumOperands().
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assert((isImpReg || MCID->isVariadic() || OpNo < MCID->getNumOperands()) &&
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// RegMask operands go between the explicit and implicit operands.
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assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
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OpNo < MCID->getNumOperands()) &&
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"Trying to add an operand to a machine instr that is already done!");
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// All operands from OpNo have been removed from RegInfo. If the Operands
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@ -48,16 +48,31 @@ unsigned InstrEmitter::CountResults(SDNode *Node) {
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return N;
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}
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/// CountOperands - The inputs to target nodes have any actual inputs first,
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/// countOperands - The inputs to target nodes have any actual inputs first,
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/// followed by an optional chain operand, then an optional glue operand.
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/// Compute the number of actual operands that will go into the resulting
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/// MachineInstr.
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unsigned InstrEmitter::CountOperands(SDNode *Node) {
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///
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/// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
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/// the chain and glue. These operands may be implicit on the machine instr.
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static unsigned countOperands(SDNode *Node, unsigned &NumImpUses) {
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unsigned N = Node->getNumOperands();
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while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
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--N;
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if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
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--N; // Ignore chain if it exists.
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// Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
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for (unsigned I = N; I; --I) {
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if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
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continue;
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if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
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if (TargetRegisterInfo::isPhysicalRegister(RN->getReg()))
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continue;
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NumImpUses = N - I;
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break;
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}
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return N;
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}
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@ -337,8 +352,7 @@ InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
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/// AddOperand - Add the specified operand to the specified machine instr. II
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/// specifies the instruction information for the node, and IIOpNum is the
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/// operand number (in the II) that we are adding. IIOpNum and II are used for
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/// assertions only.
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/// operand number (in the II) that we are adding.
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void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
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unsigned IIOpNum,
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const MCInstrDesc *II,
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@ -353,7 +367,11 @@ void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
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const ConstantFP *CFP = F->getConstantFPValue();
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MI->addOperand(MachineOperand::CreateFPImm(CFP));
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} else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
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// Turn additional physreg operands into implicit uses on non-variadic
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// instructions. This is used by call and return instructions passing
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// arguments in registers.
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bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
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MI->addOperand(MachineOperand::CreateReg(R->getReg(), false, Imp));
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} else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
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MI->addOperand(MachineOperand::CreateRegMask(RM->getRegMask()));
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} else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
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@ -696,7 +714,8 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
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const MCInstrDesc &II = TII->get(Opc);
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unsigned NumResults = CountResults(Node);
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unsigned NodeOperands = CountOperands(Node);
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unsigned NumImpUses = 0;
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unsigned NodeOperands = countOperands(Node, NumImpUses);
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bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0;
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#ifndef NDEBUG
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unsigned NumMIOperands = NodeOperands + NumResults;
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@ -705,7 +724,8 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
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"Too few operands for a variadic node!");
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else
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assert(NumMIOperands >= II.getNumOperands() &&
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NumMIOperands <= II.getNumOperands()+II.getNumImplicitDefs() &&
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NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
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NumImpUses &&
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"#operands for dag node doesn't match .td file!");
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#endif
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@ -105,12 +105,6 @@ public:
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/// (which do not go into the machine instrs.)
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static unsigned CountResults(SDNode *Node);
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/// CountOperands - The inputs to target nodes have any actual inputs first,
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/// followed by an optional chain operand, then flag operands. Compute
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/// the number of actual operands that will go into the resulting
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/// MachineInstr.
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static unsigned CountOperands(SDNode *Node);
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/// EmitDbgValue - Generate machine instruction for a dbg_value node.
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///
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MachineInstr *EmitDbgValue(SDDbgValue *SD,
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