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Fix test cases.

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Generate code for Mips32r1 unless a Mips32r2 feature is tested.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139433 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-09-09 23:14:58 +00:00
parent 921d01ae1f
commit 33ff5aeaa8
15 changed files with 53 additions and 53 deletions
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2
test/CodeGen/Mips/2010-11-09-CountLeading.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
; RUN: llc -march=mips < %s | FileCheck %s
; CHECK: clz $2, $4
define i32 @t1(i32 %X) nounwind readnone {

2
test/CodeGen/Mips/2010-11-09-Mul.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
; RUN: llc -march=mips < %s | FileCheck %s
; CHECK: mul $2, $5, $4
define i32 @mul1(i32 %a, i32 %b) nounwind readnone {

2
test/CodeGen/Mips/alloca.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
; RUN: llc -march=mipsel < %s | FileCheck %s
define i32 @twoalloca(i32 %size) nounwind {
entry:

4
test/CodeGen/Mips/cmov.ll
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@ -1,5 +1,5 @@
; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
; RUN: llc -march=mips -mcpu=4ke -regalloc=basic < %s | FileCheck %s
; RUN: llc -march=mips < %s | FileCheck %s
; RUN: llc -march=mips -regalloc=basic < %s | FileCheck %s
@i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
@i3 = common global i32* null, align 4

2
test/CodeGen/Mips/double2int.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
; RUN: llc -march=mips < %s | FileCheck %s
define i32 @f1(double %d) nounwind readnone {
entry:

4
test/CodeGen/Mips/eh.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EL
; RUN: llc < %s -march=mips -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EB
; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-EL
; RUN: llc < %s -march=mips | FileCheck %s -check-prefix=CHECK-EB
@g1 = global double 0.000000e+00, align 8
@_ZTId = external constant i8*

4
test/CodeGen/Mips/fcopysign.ll
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@ -1,5 +1,5 @@
; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EL
; RUN: llc < %s -march=mips -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EB
; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-EL
; RUN: llc < %s -march=mips | FileCheck %s -check-prefix=CHECK-EB
define double @func0(double %d0, double %d1) nounwind readnone {
entry:

10
test/CodeGen/Mips/fpcmp.ll
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@ -1,13 +1,13 @@
; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2
; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-MIPS32
@g1 = external global i32
define i32 @f(float %f0, float %f1) nounwind {
entry:
; CHECK-MIPS32R2: c.olt.s
; CHECK-MIPS32R2: movt
; CHECK-MIPS32R2: c.olt.s
; CHECK-MIPS32R2: movt
; CHECK-MIPS32: c.olt.s
; CHECK-MIPS32: movt
; CHECK-MIPS32: c.olt.s
; CHECK-MIPS32: movt
%cmp = fcmp olt float %f0, %f1
%conv = zext i1 %cmp to i32
%tmp2 = load i32* @g1, align 4

2
test/CodeGen/Mips/i64arg.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
; RUN: llc -march=mips < %s | FileCheck %s
define void @f1(i64 %ll1, float %f, i64 %ll, i32 %i, float %f2) nounwind {
entry:

2
test/CodeGen/Mips/inlineasmmemop.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
; RUN: llc -march=mipsel < %s | FileCheck %s
@g1 = external global i32

2
test/CodeGen/Mips/internalfunc.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s
; RUN: llc < %s -march=mipsel | FileCheck %s
@caller.sf1 = internal unnamed_addr global void (...)* null, align 4
@gf1 = external global void (...)*

2
test/CodeGen/Mips/madd-msub.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
; RUN: llc -march=mips < %s | FileCheck %s
; CHECK: madd $5, $4
define i64 @madd1(i32 %a, i32 %b, i32 %c) nounwind readnone {

2
test/CodeGen/Mips/o32_cc.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s
; RUN: llc -march=mips < %s | FileCheck %s
; FIXME: Disabled because it unpredictably fails on certain platforms.
; REQUIRES: disabled

2
test/CodeGen/Mips/o32_cc_byval.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
; RUN: llc -march=mipsel < %s | FileCheck %s
%0 = type { i8, i16, i32, i64, double, i32, [4 x i8] }
%struct.S1 = type { i8, i16, i32, i64, double, i32 }

64
test/CodeGen/Mips/select.ll
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@ -1,11 +1,11 @@
; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2
; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK
@d2 = external global double
@d3 = external global double
define i32 @sel1(i32 %s, i32 %f0, i32 %f1) nounwind readnone {
entry:
; CHECK-MIPS32R2: movn
; CHECK: movn
%tobool = icmp ne i32 %s, 0
%cond = select i1 %tobool, i32 %f1, i32 %f0
ret i32 %cond
@ -13,7 +13,7 @@ entry:
define float @sel2(i32 %s, float %f0, float %f1) nounwind readnone {
entry:
; CHECK-MIPS32R2: movn.s
; CHECK: movn.s
%tobool = icmp ne i32 %s, 0
%cond = select i1 %tobool, float %f0, float %f1
ret float %cond
@ -21,7 +21,7 @@ entry:
define double @sel2_1(i32 %s, double %f0, double %f1) nounwind readnone {
entry:
; CHECK-MIPS32R2: movn.d
; CHECK: movn.d
%tobool = icmp ne i32 %s, 0
%cond = select i1 %tobool, double %f0, double %f1
ret double %cond
@ -29,8 +29,8 @@ entry:
define float @sel3(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
entry:
; CHECK-MIPS32R2: c.eq.s
; CHECK-MIPS32R2: movt.s
; CHECK: c.eq.s
; CHECK: movt.s
%cmp = fcmp oeq float %f2, %f3
%cond = select i1 %cmp, float %f0, float %f1
ret float %cond
@ -38,8 +38,8 @@ entry:
define float @sel4(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
entry:
; CHECK-MIPS32R2: c.olt.s
; CHECK-MIPS32R2: movt.s
; CHECK: c.olt.s
; CHECK: movt.s
%cmp = fcmp olt float %f2, %f3
%cond = select i1 %cmp, float %f0, float %f1
ret float %cond
@ -47,8 +47,8 @@ entry:
define float @sel5(float %f0, float %f1, float %f2, float %f3) nounwind readnone {
entry:
; CHECK-MIPS32R2: c.ule.s
; CHECK-MIPS32R2: movf.s
; CHECK: c.ule.s
; CHECK: movf.s
%cmp = fcmp ogt float %f2, %f3
%cond = select i1 %cmp, float %f0, float %f1
ret float %cond
@ -56,8 +56,8 @@ entry:
define double @sel5_1(double %f0, double %f1, float %f2, float %f3) nounwind readnone {
entry:
; CHECK-MIPS32R2: c.ule.s
; CHECK-MIPS32R2: movf.d
; CHECK: c.ule.s
; CHECK: movf.d
%cmp = fcmp ogt float %f2, %f3
%cond = select i1 %cmp, double %f0, double %f1
ret double %cond
@ -65,8 +65,8 @@ entry:
define double @sel6(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
entry:
; CHECK-MIPS32R2: c.eq.d
; CHECK-MIPS32R2: movt.d
; CHECK: c.eq.d
; CHECK: movt.d
%cmp = fcmp oeq double %f2, %f3
%cond = select i1 %cmp, double %f0, double %f1
ret double %cond
@ -74,8 +74,8 @@ entry:
define double @sel7(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
entry:
; CHECK-MIPS32R2: c.olt.d
; CHECK-MIPS32R2: movt.d
; CHECK: c.olt.d
; CHECK: movt.d
%cmp = fcmp olt double %f2, %f3
%cond = select i1 %cmp, double %f0, double %f1
ret double %cond
@ -83,8 +83,8 @@ entry:
define double @sel8(double %f0, double %f1, double %f2, double %f3) nounwind readnone {
entry:
; CHECK-MIPS32R2: c.ule.d
; CHECK-MIPS32R2: movf.d
; CHECK: c.ule.d
; CHECK: movf.d
%cmp = fcmp ogt double %f2, %f3
%cond = select i1 %cmp, double %f0, double %f1
ret double %cond
@ -92,8 +92,8 @@ entry:
define float @sel8_1(float %f0, float %f1, double %f2, double %f3) nounwind readnone {
entry:
; CHECK-MIPS32R2: c.ule.d
; CHECK-MIPS32R2: movf.s
; CHECK: c.ule.d
; CHECK: movf.s
%cmp = fcmp ogt double %f2, %f3
%cond = select i1 %cmp, float %f0, float %f1
ret float %cond
@ -101,8 +101,8 @@ entry:
define i32 @sel9(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone {
entry:
; CHECK-MIPS32R2: c.eq.s
; CHECK-MIPS32R2: movt
; CHECK: c.eq.s
; CHECK: movt
%cmp = fcmp oeq float %f2, %f3
%cond = select i1 %cmp, i32 %f0, i32 %f1
ret i32 %cond
@ -110,8 +110,8 @@ entry:
define i32 @sel10(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone {
entry:
; CHECK-MIPS32R2: c.olt.s
; CHECK-MIPS32R2: movt
; CHECK: c.olt.s
; CHECK: movt
%cmp = fcmp olt float %f2, %f3
%cond = select i1 %cmp, i32 %f0, i32 %f1
ret i32 %cond
@ -119,8 +119,8 @@ entry:
define i32 @sel11(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone {
entry:
; CHECK-MIPS32R2: c.ule.s
; CHECK-MIPS32R2: movf
; CHECK: c.ule.s
; CHECK: movf
%cmp = fcmp ogt float %f2, %f3
%cond = select i1 %cmp, i32 %f0, i32 %f1
ret i32 %cond
@ -128,8 +128,8 @@ entry:
define i32 @sel12(i32 %f0, i32 %f1) nounwind readonly {
entry:
; CHECK-MIPS32R2: c.eq.d
; CHECK-MIPS32R2: movt
; CHECK: c.eq.d
; CHECK: movt
%tmp = load double* @d2, align 8, !tbaa !0
%tmp1 = load double* @d3, align 8, !tbaa !0
%cmp = fcmp oeq double %tmp, %tmp1
@ -139,8 +139,8 @@ entry:
define i32 @sel13(i32 %f0, i32 %f1) nounwind readonly {
entry:
; CHECK-MIPS32R2: c.olt.d
; CHECK-MIPS32R2: movt
; CHECK: c.olt.d
; CHECK: movt
%tmp = load double* @d2, align 8, !tbaa !0
%tmp1 = load double* @d3, align 8, !tbaa !0
%cmp = fcmp olt double %tmp, %tmp1
@ -150,8 +150,8 @@ entry:
define i32 @sel14(i32 %f0, i32 %f1) nounwind readonly {
entry:
; CHECK-MIPS32R2: c.ule.d
; CHECK-MIPS32R2: movf
; CHECK: c.ule.d
; CHECK: movf
%tmp = load double* @d2, align 8, !tbaa !0
%tmp1 = load double* @d3, align 8, !tbaa !0
%cmp = fcmp ogt double %tmp, %tmp1