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https://github.com/c64scene-ar/llvm-6502.git
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Add feature flags for AVX and FMA and fix some SSE4A feature flag
initialization problems. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74350 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -55,6 +55,13 @@ def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
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def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
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def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
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"Support SSE 4a instructions">;
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"Support SSE 4a instructions">;
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def FeatureAVX : SubtargetFeature<"avx", "HasAVX", "true",
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"Enable AVX instructions">;
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def FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true",
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"Enable three-operand fused multiple-add">;
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def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
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"Enable four-operand fused multiple-add">;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// X86 processors supported.
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// X86 processors supported.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@@ -82,6 +89,9 @@ def : Proc<"core2", [FeatureSSSE3, Feature64Bit, FeatureSlowBTMem]>;
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def : Proc<"penryn", [FeatureSSE41, Feature64Bit, FeatureSlowBTMem]>;
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def : Proc<"penryn", [FeatureSSE41, Feature64Bit, FeatureSlowBTMem]>;
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def : Proc<"atom", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>;
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def : Proc<"atom", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>;
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def : Proc<"corei7", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem]>;
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def : Proc<"corei7", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem]>;
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def : Proc<"nehalem", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem]>;
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// Sandy Bridge does not have FMA
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def : Proc<"sandybridge", [FeatureSSE42, FeatureAVX, Feature64Bit]>;
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def : Proc<"k6", [FeatureMMX]>;
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def : Proc<"k6", [FeatureMMX]>;
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def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>;
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def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>;
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@@ -236,6 +236,10 @@ def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
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def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
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def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
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def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
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def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
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def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
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def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
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def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
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def HasAVX : Predicate<"Subtarget->hasAVX()">;
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def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
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def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
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def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
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def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
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def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
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def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
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def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
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def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
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@@ -207,6 +207,10 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
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bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
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bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
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bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
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bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
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HasFMA3 = IsIntel && ((ECX >> 12) & 0x1);
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HasAVX = ((ECX >> 28) & 0x1);
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if (IsIntel || IsAMD) {
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if (IsIntel || IsAMD) {
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// Determine if bit test memory instructions are slow.
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// Determine if bit test memory instructions are slow.
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unsigned Family = 0;
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unsigned Family = 0;
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@@ -217,6 +221,7 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
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X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
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X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
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HasX86_64 = (EDX >> 29) & 0x1;
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HasX86_64 = (EDX >> 29) & 0x1;
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HasSSE4A = IsAMD && ((ECX >> 6) & 0x1);
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HasSSE4A = IsAMD && ((ECX >> 6) & 0x1);
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HasFMA4 = IsAMD && ((ECX >> 16) & 0x1);
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}
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}
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}
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}
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@@ -342,6 +347,10 @@ X86Subtarget::X86Subtarget(const Module &M, const std::string &FS, bool is64Bit)
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, X86SSELevel(NoMMXSSE)
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, X86SSELevel(NoMMXSSE)
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, X863DNowLevel(NoThreeDNow)
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, X863DNowLevel(NoThreeDNow)
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, HasX86_64(false)
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, HasX86_64(false)
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, HasSSE4A(false)
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, HasAVX(false)
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, HasFMA3(false)
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, HasFMA4(false)
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, IsBTMemSlow(false)
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, IsBTMemSlow(false)
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, DarwinVers(0)
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, DarwinVers(0)
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, IsLinux(false)
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, IsLinux(false)
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@@ -64,12 +64,21 @@ protected:
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///
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///
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bool HasX86_64;
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bool HasX86_64;
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/// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
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bool IsBTMemSlow;
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/// HasSSE4A - True if the processor supports SSE4A instructions.
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/// HasSSE4A - True if the processor supports SSE4A instructions.
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bool HasSSE4A;
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bool HasSSE4A;
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/// HasAVX - Target has AVX instructions
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bool HasAVX;
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/// HasFMA3 - Target has 3-operand fused multiply-add
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bool HasFMA3;
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/// HasFMA4 - Target has 4-operand fused multiply-add
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bool HasFMA4;
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/// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
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bool IsBTMemSlow;
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/// DarwinVers - Nonzero if this is a darwin platform: the numeric
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/// DarwinVers - Nonzero if this is a darwin platform: the numeric
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/// version of the platform, e.g. 8 = 10.4 (Tiger), 9 = 10.5 (Leopard), etc.
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/// version of the platform, e.g. 8 = 10.4 (Tiger), 9 = 10.5 (Leopard), etc.
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unsigned char DarwinVers; // Is any darwin-x86 platform.
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unsigned char DarwinVers; // Is any darwin-x86 platform.
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@@ -133,6 +142,9 @@ public:
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bool hasSSE4A() const { return HasSSE4A; }
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bool hasSSE4A() const { return HasSSE4A; }
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bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
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bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
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bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
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bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
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bool hasAVX() const { return hasAVX(); }
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bool hasFMA3() const { return HasFMA3; }
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bool hasFMA4() const { return HasFMA4; }
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bool isBTMemSlow() const { return IsBTMemSlow; }
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bool isBTMemSlow() const { return IsBTMemSlow; }
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