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Fix another case of <rdar://problem/9184212> that only occurs with code

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generated by llvm-gcc, since llvm-gcc uses 2 i64s for passing a 4 x float
vector on ARM rather than an i64 array like Clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129878 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Cameron Zwarich
2011-04-20 21:48:38 +00:00
parent c5c43b958c
commit 344731c018
2 changed files with 57 additions and 29 deletions
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15
test/Transforms/ScalarRepl/vector_promote.ll
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@@ -248,3 +248,18 @@ entry:
; CHECK: shufflevector <4 x i64> %tmpV2, <4 x i64> undef, <3 x i32> <i32 0, i32 1, i32 2>
}
define <4 x float> @test16(<4 x float> %x, i64 %y0, i64 %y1) {
entry:
%tmp8 = bitcast <4 x float> undef to <2 x double>
%tmp9 = bitcast i64 %y0 to double
%tmp10 = insertelement <2 x double> %tmp8, double %tmp9, i32 0
%tmp11 = bitcast <2 x double> %tmp10 to <4 x float>
%tmp3 = bitcast <4 x float> %tmp11 to <2 x double>
%tmp4 = bitcast i64 %y1 to double
%tmp5 = insertelement <2 x double> %tmp3, double %tmp4, i32 1
%tmp6 = bitcast <2 x double> %tmp5 to <4 x float>
ret <4 x float> %tmp6
; CHECK: @test16
; CHECK-NOT: alloca
; CHECK: bitcast <4 x float> %tmp11 to <2 x double>
}