mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-12 07:37:34 +00:00
Merge floating point and integer UNPCK X86ISD node types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145926 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
18851edbc4
commit
34671b812a
@ -2851,10 +2851,8 @@ static bool isTargetShuffle(unsigned Opcode) {
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case X86ISD::MOVDDUP:
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case X86ISD::MOVSS:
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case X86ISD::MOVSD:
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case X86ISD::UNPCKLP:
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case X86ISD::PUNPCKL:
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case X86ISD::UNPCKHP:
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case X86ISD::PUNPCKH:
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case X86ISD::UNPCKL:
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case X86ISD::UNPCKH:
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case X86ISD::VPERMILP:
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case X86ISD::VPERM2X128:
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return true;
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@ -2914,10 +2912,8 @@ static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
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case X86ISD::MOVLPD:
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case X86ISD::MOVSS:
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case X86ISD::MOVSD:
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case X86ISD::UNPCKLP:
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case X86ISD::PUNPCKL:
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case X86ISD::UNPCKHP:
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case X86ISD::PUNPCKH:
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case X86ISD::UNPCKL:
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case X86ISD::UNPCKH:
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return DAG.getNode(Opc, dl, VT, V1, V2);
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}
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return SDValue();
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@ -4460,12 +4456,10 @@ static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
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DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
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ShuffleMask);
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break;
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case X86ISD::PUNPCKH:
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case X86ISD::UNPCKHP:
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case X86ISD::UNPCKH:
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DecodeUNPCKHMask(VT, ShuffleMask);
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break;
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case X86ISD::PUNPCKL:
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case X86ISD::UNPCKLP:
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case X86ISD::UNPCKL:
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DecodeUNPCKLMask(VT, ShuffleMask);
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break;
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case X86ISD::MOVHLPS:
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@ -6364,50 +6358,6 @@ SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasXMMInt) {
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X86::getShuffleSHUFImmediate(SVOp), DAG);
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}
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static inline unsigned getUNPCKLOpcode(EVT VT, bool HasAVX2) {
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switch(VT.getSimpleVT().SimpleTy) {
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case MVT::v32i8:
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case MVT::v16i8:
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case MVT::v16i16:
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case MVT::v8i16:
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case MVT::v4i32:
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case MVT::v2i64: return X86ISD::PUNPCKL;
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case MVT::v8i32:
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case MVT::v4i64:
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if (HasAVX2) return X86ISD::PUNPCKL;
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// else use fp unit for int unpack.
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case MVT::v8f32:
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case MVT::v4f32:
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case MVT::v4f64:
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case MVT::v2f64: return X86ISD::UNPCKLP;
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default:
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llvm_unreachable("Unknown type for unpckl");
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}
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return 0;
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}
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static inline unsigned getUNPCKHOpcode(EVT VT, bool HasAVX2) {
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switch(VT.getSimpleVT().SimpleTy) {
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case MVT::v32i8:
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case MVT::v16i8:
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case MVT::v16i16:
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case MVT::v8i16:
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case MVT::v4i32:
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case MVT::v2i64: return X86ISD::PUNPCKH;
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case MVT::v4i64:
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case MVT::v8i32:
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if (HasAVX2) return X86ISD::PUNPCKH;
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// else use fp unit for int unpack.
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case MVT::v8f32:
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case MVT::v4f32:
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case MVT::v4f64:
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case MVT::v2f64: return X86ISD::UNPCKHP;
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default:
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llvm_unreachable("Unknown type for unpckh");
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}
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return 0;
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}
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static
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SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
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const TargetLowering &TLI,
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@ -6518,11 +6468,9 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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// NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
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// unpckh_undef). Only use pshufd if speed is more important than size.
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if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
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return getTargetShuffleNode(getUNPCKLOpcode(VT, HasAVX2), dl, VT, V1, V1,
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DAG);
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return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
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if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
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return getTargetShuffleNode(getUNPCKHOpcode(VT, HasAVX2), dl, VT, V1, V1,
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DAG);
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return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
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if (X86::isMOVDDUPMask(SVOp) && Subtarget->hasSSE3orAVX() &&
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V2IsUndef && RelaxedMayFoldVectorLoad(V1))
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@ -6534,8 +6482,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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// Use to match splats
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if (HasXMMInt && X86::isUNPCKHMask(SVOp, HasAVX2) && V2IsUndef &&
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(VT == MVT::v2f64 || VT == MVT::v2i64))
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return getTargetShuffleNode(getUNPCKHOpcode(VT, HasAVX2), dl, VT, V1, V1,
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DAG);
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return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
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if (X86::isPSHUFDMask(SVOp)) {
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// The actual implementation will match the mask in the if above and then
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@ -6635,12 +6582,10 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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}
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if (isUNPCKLMask(M, VT, HasAVX2))
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return getTargetShuffleNode(getUNPCKLOpcode(VT, HasAVX2), dl, VT, V1, V2,
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DAG);
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return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
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if (isUNPCKHMask(M, VT, HasAVX2))
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return getTargetShuffleNode(getUNPCKHOpcode(VT, HasAVX2), dl, VT, V1, V2,
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DAG);
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return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
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if (V2IsSplat) {
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// Normalize mask so all entries that point to V2 points to its first
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@ -6664,12 +6609,10 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
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if (X86::isUNPCKLMask(NewSVOp, HasAVX2))
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return getTargetShuffleNode(getUNPCKLOpcode(VT, HasAVX2), dl, VT, V2, V1,
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DAG);
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return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V2, V1, DAG);
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if (X86::isUNPCKHMask(NewSVOp, HasAVX2))
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return getTargetShuffleNode(getUNPCKHOpcode(VT, HasAVX2), dl, VT, V2, V1,
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DAG);
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return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V2, V1, DAG);
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}
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// Normalize the node to match x86 shuffle ops if needed
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@ -6689,8 +6632,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
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SVOp->getSplatIndex() == 0 && V2IsUndef) {
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if (VT == MVT::v2f64 || VT == MVT::v2i64)
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return getTargetShuffleNode(getUNPCKLOpcode(VT, HasAVX2), dl, VT, V1, V1,
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DAG);
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return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
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}
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if (isPSHUFHWMask(M, VT))
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@ -6708,11 +6650,9 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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X86::getShuffleSHUFImmediate(SVOp), DAG);
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if (isUNPCKL_v_undef_Mask(M, VT))
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return getTargetShuffleNode(getUNPCKLOpcode(VT, HasAVX2), dl, VT, V1, V1,
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DAG);
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return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
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if (isUNPCKH_v_undef_Mask(M, VT))
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return getTargetShuffleNode(getUNPCKHOpcode(VT, HasAVX2), dl, VT, V1, V1,
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DAG);
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return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
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//===--------------------------------------------------------------------===//
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// Generate target specific nodes for 128 or 256-bit shuffles only
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@ -11023,10 +10963,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
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case X86ISD::MOVSD: return "X86ISD::MOVSD";
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case X86ISD::MOVSS: return "X86ISD::MOVSS";
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case X86ISD::UNPCKLP: return "X86ISD::UNPCKLP";
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case X86ISD::UNPCKHP: return "X86ISD::UNPCKHP";
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case X86ISD::PUNPCKL: return "X86ISD::PUNPCKL";
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case X86ISD::PUNPCKH: return "X86ISD::PUNPCKH";
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case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
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case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
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case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
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case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
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case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
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@ -14616,10 +14554,8 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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case X86ISD::SHUFPS: // Handle all target specific shuffles
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case X86ISD::SHUFPD:
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case X86ISD::PALIGN:
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case X86ISD::PUNPCKH:
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case X86ISD::UNPCKHP:
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case X86ISD::PUNPCKL:
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case X86ISD::UNPCKLP:
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case X86ISD::UNPCKH:
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case X86ISD::UNPCKL:
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case X86ISD::MOVHLPS:
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case X86ISD::MOVLHPS:
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case X86ISD::PSHUFD:
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@ -273,10 +273,8 @@ namespace llvm {
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MOVLPD,
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MOVSD,
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MOVSS,
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UNPCKLP,
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UNPCKHP,
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PUNPCKL,
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PUNPCKH,
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UNPCKL,
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UNPCKH,
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VPERMILP,
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VPERM2X128,
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VBROADCAST,
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@ -130,11 +130,8 @@ def X86Movhlpd : SDNode<"X86ISD::MOVHLPD", SDTShuff2Op>;
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def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
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def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
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def X86Unpcklp : SDNode<"X86ISD::UNPCKLP", SDTShuff2Op>;
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def X86Unpckhp : SDNode<"X86ISD::UNPCKHP", SDTShuff2Op>;
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def X86Punpckl : SDNode<"X86ISD::PUNPCKL", SDTShuff2Op>;
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def X86Punpckh : SDNode<"X86ISD::PUNPCKH", SDTShuff2Op>;
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def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
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def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
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def X86VPermilp : SDNode<"X86ISD::VPERMILP", SDTShuff2OpI>;
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@ -1157,11 +1157,11 @@ let Predicates = [HasAVX] in {
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(bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
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(VMOVHPSrm VR128:$src1, addr:$src2)>;
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// FIXME: Instead of X86Unpcklp, there should be a X86Movlhpd here, the problem
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// FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
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// is during lowering, where it's not possible to recognize the load fold cause
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// it has two uses through a bitcast. One use disappears at isel time and the
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// fold opportunity reappears.
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def : Pat<(v2f64 (X86Unpcklp VR128:$src1,
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def : Pat<(v2f64 (X86Unpckl VR128:$src1,
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(scalar_to_vector (loadf64 addr:$src2)))),
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(VMOVHPDrm VR128:$src1, addr:$src2)>;
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@ -1172,10 +1172,10 @@ let Predicates = [HasAVX] in {
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// Store patterns
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def : Pat<(store (f64 (vector_extract
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(v2f64 (X86Unpckhp VR128:$src, (undef))), (iPTR 0))), addr:$dst),
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(v2f64 (X86Unpckh VR128:$src, (undef))), (iPTR 0))), addr:$dst),
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(VMOVHPSmr addr:$dst, VR128:$src)>;
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def : Pat<(store (f64 (vector_extract
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(v2f64 (X86Unpckhp VR128:$src, (undef))), (iPTR 0))), addr:$dst),
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(v2f64 (X86Unpckh VR128:$src, (undef))), (iPTR 0))), addr:$dst),
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(VMOVHPDmr addr:$dst, VR128:$src)>;
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}
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@ -1195,16 +1195,16 @@ let Predicates = [HasSSE1] in {
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// Store patterns
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def : Pat<(store (f64 (vector_extract
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(v2f64 (X86Unpckhp VR128:$src, (undef))), (iPTR 0))), addr:$dst),
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(v2f64 (X86Unpckh VR128:$src, (undef))), (iPTR 0))), addr:$dst),
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(MOVHPSmr addr:$dst, VR128:$src)>;
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}
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let Predicates = [HasSSE2] in {
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// FIXME: Instead of X86Unpcklp, there should be a X86Movlhpd here, the problem
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// FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
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// is during lowering, where it's not possible to recognize the load fold cause
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// it has two uses through a bitcast. One use disappears at isel time and the
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// fold opportunity reappears.
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def : Pat<(v2f64 (X86Unpcklp VR128:$src1,
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def : Pat<(v2f64 (X86Unpckl VR128:$src1,
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(scalar_to_vector (loadf64 addr:$src2)))),
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(MOVHPDrm VR128:$src1, addr:$src2)>;
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@ -1215,7 +1215,7 @@ let Predicates = [HasSSE2] in {
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// Store patterns
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def : Pat<(store (f64 (vector_extract
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(v2f64 (X86Unpckhp VR128:$src, (undef))), (iPTR 0))),addr:$dst),
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(v2f64 (X86Unpckh VR128:$src, (undef))), (iPTR 0))),addr:$dst),
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(MOVHPDmr addr:$dst, VR128:$src)>;
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}
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@ -2431,27 +2431,27 @@ let AddedComplexity = 10 in {
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} // AddedComplexity
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let Predicates = [HasSSE1] in {
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def : Pat<(v4f32 (X86Unpcklp VR128:$src1, (memopv4f32 addr:$src2))),
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def : Pat<(v4f32 (X86Unpckl VR128:$src1, (memopv4f32 addr:$src2))),
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(UNPCKLPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4f32 (X86Unpcklp VR128:$src1, VR128:$src2)),
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def : Pat<(v4f32 (X86Unpckl VR128:$src1, VR128:$src2)),
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(UNPCKLPSrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v4f32 (X86Unpckhp VR128:$src1, (memopv4f32 addr:$src2))),
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def : Pat<(v4f32 (X86Unpckh VR128:$src1, (memopv4f32 addr:$src2))),
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(UNPCKHPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4f32 (X86Unpckhp VR128:$src1, VR128:$src2)),
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def : Pat<(v4f32 (X86Unpckh VR128:$src1, VR128:$src2)),
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(UNPCKHPSrr VR128:$src1, VR128:$src2)>;
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}
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let Predicates = [HasSSE2] in {
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def : Pat<(v2f64 (X86Unpcklp VR128:$src1, (memopv2f64 addr:$src2))),
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def : Pat<(v2f64 (X86Unpckl VR128:$src1, (memopv2f64 addr:$src2))),
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(UNPCKLPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2f64 (X86Unpcklp VR128:$src1, VR128:$src2)),
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def : Pat<(v2f64 (X86Unpckl VR128:$src1, VR128:$src2)),
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(UNPCKLPDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v2f64 (X86Unpckhp VR128:$src1, (memopv2f64 addr:$src2))),
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def : Pat<(v2f64 (X86Unpckh VR128:$src1, (memopv2f64 addr:$src2))),
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(UNPCKHPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2f64 (X86Unpckhp VR128:$src1, VR128:$src2)),
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def : Pat<(v2f64 (X86Unpckh VR128:$src1, VR128:$src2)),
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(UNPCKHPDrr VR128:$src1, VR128:$src2)>;
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// FIXME: Instead of X86Movddup, there should be a X86Unpcklp here, the
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// FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
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// problem is during lowering, where it's not possible to recognize the load
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// fold cause it has two uses through a bitcast. One use disappears at isel
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// time and the fold opportunity reappears.
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@ -2464,59 +2464,43 @@ let Predicates = [HasSSE2] in {
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}
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let Predicates = [HasAVX] in {
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def : Pat<(v4f32 (X86Unpcklp VR128:$src1, (memopv4f32 addr:$src2))),
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def : Pat<(v4f32 (X86Unpckl VR128:$src1, (memopv4f32 addr:$src2))),
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(VUNPCKLPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4f32 (X86Unpcklp VR128:$src1, VR128:$src2)),
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def : Pat<(v4f32 (X86Unpckl VR128:$src1, VR128:$src2)),
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(VUNPCKLPSrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v4f32 (X86Unpckhp VR128:$src1, (memopv4f32 addr:$src2))),
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def : Pat<(v4f32 (X86Unpckh VR128:$src1, (memopv4f32 addr:$src2))),
|
||||
(VUNPCKHPSrm VR128:$src1, addr:$src2)>;
|
||||
def : Pat<(v4f32 (X86Unpckhp VR128:$src1, VR128:$src2)),
|
||||
def : Pat<(v4f32 (X86Unpckh VR128:$src1, VR128:$src2)),
|
||||
(VUNPCKHPSrr VR128:$src1, VR128:$src2)>;
|
||||
|
||||
def : Pat<(v8f32 (X86Unpcklp VR256:$src1, (memopv8f32 addr:$src2))),
|
||||
def : Pat<(v8f32 (X86Unpckl VR256:$src1, (memopv8f32 addr:$src2))),
|
||||
(VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
|
||||
def : Pat<(v8f32 (X86Unpcklp VR256:$src1, VR256:$src2)),
|
||||
def : Pat<(v8f32 (X86Unpckl VR256:$src1, VR256:$src2)),
|
||||
(VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
|
||||
def : Pat<(v8i32 (X86Unpcklp VR256:$src1, VR256:$src2)),
|
||||
(VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
|
||||
def : Pat<(v8i32 (X86Unpcklp VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
|
||||
(VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
|
||||
def : Pat<(v8f32 (X86Unpckhp VR256:$src1, (memopv8f32 addr:$src2))),
|
||||
def : Pat<(v8f32 (X86Unpckh VR256:$src1, (memopv8f32 addr:$src2))),
|
||||
(VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
|
||||
def : Pat<(v8f32 (X86Unpckhp VR256:$src1, VR256:$src2)),
|
||||
(VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
|
||||
def : Pat<(v8i32 (X86Unpckhp VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
|
||||
(VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
|
||||
def : Pat<(v8i32 (X86Unpckhp VR256:$src1, VR256:$src2)),
|
||||
def : Pat<(v8f32 (X86Unpckh VR256:$src1, VR256:$src2)),
|
||||
(VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
|
||||
|
||||
def : Pat<(v2f64 (X86Unpcklp VR128:$src1, (memopv2f64 addr:$src2))),
|
||||
def : Pat<(v2f64 (X86Unpckl VR128:$src1, (memopv2f64 addr:$src2))),
|
||||
(VUNPCKLPDrm VR128:$src1, addr:$src2)>;
|
||||
def : Pat<(v2f64 (X86Unpcklp VR128:$src1, VR128:$src2)),
|
||||
def : Pat<(v2f64 (X86Unpckl VR128:$src1, VR128:$src2)),
|
||||
(VUNPCKLPDrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(v2f64 (X86Unpckhp VR128:$src1, (memopv2f64 addr:$src2))),
|
||||
def : Pat<(v2f64 (X86Unpckh VR128:$src1, (memopv2f64 addr:$src2))),
|
||||
(VUNPCKHPDrm VR128:$src1, addr:$src2)>;
|
||||
def : Pat<(v2f64 (X86Unpckhp VR128:$src1, VR128:$src2)),
|
||||
def : Pat<(v2f64 (X86Unpckh VR128:$src1, VR128:$src2)),
|
||||
(VUNPCKHPDrr VR128:$src1, VR128:$src2)>;
|
||||
|
||||
def : Pat<(v4f64 (X86Unpcklp VR256:$src1, (memopv4f64 addr:$src2))),
|
||||
def : Pat<(v4f64 (X86Unpckl VR256:$src1, (memopv4f64 addr:$src2))),
|
||||
(VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
|
||||
def : Pat<(v4f64 (X86Unpcklp VR256:$src1, VR256:$src2)),
|
||||
def : Pat<(v4f64 (X86Unpckl VR256:$src1, VR256:$src2)),
|
||||
(VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
|
||||
def : Pat<(v4i64 (X86Unpcklp VR256:$src1, (memopv4i64 addr:$src2))),
|
||||
(VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
|
||||
def : Pat<(v4i64 (X86Unpcklp VR256:$src1, VR256:$src2)),
|
||||
(VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
|
||||
def : Pat<(v4f64 (X86Unpckhp VR256:$src1, (memopv4f64 addr:$src2))),
|
||||
def : Pat<(v4f64 (X86Unpckh VR256:$src1, (memopv4f64 addr:$src2))),
|
||||
(VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
|
||||
def : Pat<(v4f64 (X86Unpckhp VR256:$src1, VR256:$src2)),
|
||||
(VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
|
||||
def : Pat<(v4i64 (X86Unpckhp VR256:$src1, (memopv4i64 addr:$src2))),
|
||||
(VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
|
||||
def : Pat<(v4i64 (X86Unpckhp VR256:$src1, VR256:$src2)),
|
||||
def : Pat<(v4f64 (X86Unpckh VR256:$src1, VR256:$src2)),
|
||||
(VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
|
||||
|
||||
// FIXME: Instead of X86Movddup, there should be a X86Unpcklp here, the
|
||||
// FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
|
||||
// problem is during lowering, where it's not possible to recognize the load
|
||||
// fold cause it has two uses through a bitcast. One use disappears at isel
|
||||
// time and the fold opportunity reappears.
|
||||
@ -4199,66 +4183,88 @@ multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
|
||||
}
|
||||
|
||||
let Predicates = [HasAVX] in {
|
||||
defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Punpckl,
|
||||
defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
|
||||
bc_v16i8, 0>, VEX_4V;
|
||||
defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Punpckl,
|
||||
defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
|
||||
bc_v8i16, 0>, VEX_4V;
|
||||
defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Punpckl,
|
||||
defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
|
||||
bc_v4i32, 0>, VEX_4V;
|
||||
defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Punpckl,
|
||||
defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
|
||||
bc_v2i64, 0>, VEX_4V;
|
||||
|
||||
defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Punpckh,
|
||||
defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
|
||||
bc_v16i8, 0>, VEX_4V;
|
||||
defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Punpckh,
|
||||
defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
|
||||
bc_v8i16, 0>, VEX_4V;
|
||||
defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Punpckh,
|
||||
defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
|
||||
bc_v4i32, 0>, VEX_4V;
|
||||
defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Punpckh,
|
||||
defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
|
||||
bc_v2i64, 0>, VEX_4V;
|
||||
}
|
||||
|
||||
let Predicates = [HasAVX2] in {
|
||||
defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Punpckl,
|
||||
defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
|
||||
bc_v32i8>, VEX_4V;
|
||||
defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Punpckl,
|
||||
defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
|
||||
bc_v16i16>, VEX_4V;
|
||||
defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Punpckl,
|
||||
defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
|
||||
bc_v8i32>, VEX_4V;
|
||||
defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Punpckl,
|
||||
defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
|
||||
bc_v4i64>, VEX_4V;
|
||||
|
||||
defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Punpckh,
|
||||
defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
|
||||
bc_v32i8>, VEX_4V;
|
||||
defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Punpckh,
|
||||
defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
|
||||
bc_v16i16>, VEX_4V;
|
||||
defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Punpckh,
|
||||
defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
|
||||
bc_v8i32>, VEX_4V;
|
||||
defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Punpckh,
|
||||
defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
|
||||
bc_v4i64>, VEX_4V;
|
||||
}
|
||||
|
||||
let Constraints = "$src1 = $dst" in {
|
||||
defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Punpckl,
|
||||
defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
|
||||
bc_v16i8>;
|
||||
defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Punpckl,
|
||||
defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
|
||||
bc_v8i16>;
|
||||
defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Punpckl,
|
||||
defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
|
||||
bc_v4i32>;
|
||||
defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Punpckl,
|
||||
defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
|
||||
bc_v2i64>;
|
||||
|
||||
defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Punpckh,
|
||||
defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
|
||||
bc_v16i8>;
|
||||
defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Punpckh,
|
||||
defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
|
||||
bc_v8i16>;
|
||||
defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Punpckh,
|
||||
defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
|
||||
bc_v4i32>;
|
||||
defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Punpckh,
|
||||
defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
|
||||
bc_v2i64>;
|
||||
}
|
||||
} // ExeDomain = SSEPackedInt
|
||||
|
||||
// Patterns for using AVX1 instructions with integer vectors
|
||||
// Here to give AVX2 priority
|
||||
let Predicates = [HasAVX] in {
|
||||
def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
|
||||
(VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
|
||||
def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
|
||||
(VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
|
||||
def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
|
||||
(VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
|
||||
def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
|
||||
(VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
|
||||
|
||||
def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
|
||||
(VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
|
||||
def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
|
||||
(VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
|
||||
def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
|
||||
(VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
|
||||
def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
|
||||
(VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
|
||||
}
|
||||
|
||||
// Splat v2f64 / v2i64
|
||||
let AddedComplexity = 10 in {
|
||||
def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user