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Make musttail more robust for vector types on x86
Previously I tried to plug musttail into the existing vararg lowering code. That turned out to be a mistake, because non-vararg calls use significantly different register lowering, even on x86. For example, AVX vectors are usually passed in registers to normal functions and memory to vararg functions. Now musttail uses a completely separate lowering. Hopefully this can be used as the basis for non-x86 perfect forwarding. Reviewers: majnemer Differential Revision: http://reviews.llvm.org/D6156 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224745 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reid Kleckner
parent
b39244dca3
commit
34b7fde802
@ -158,6 +158,16 @@ public:
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}
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};
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/// Describes a register that needs to be forwarded from the prologue to a
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/// musttail call.
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struct ForwardedRegister {
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ForwardedRegister(unsigned VReg, MCPhysReg PReg, MVT VT)
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: VReg(VReg), PReg(PReg), VT(VT) {}
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unsigned VReg;
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MCPhysReg PReg;
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MVT VT;
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};
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/// CCAssignFn - This function assigns a location for Val, updating State to
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/// reflect the change. It returns 'true' if it failed to handle Val.
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typedef bool CCAssignFn(unsigned ValNo, MVT ValVT,
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@ -470,6 +480,19 @@ public:
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return PendingLocs;
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}
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/// Compute the remaining unused register parameters that would be used for
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/// the given value type. This is useful when varargs are passed in the
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/// registers that normal prototyped parameters would be passed in, or for
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/// implementing perfect forwarding.
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void getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, MVT VT,
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CCAssignFn Fn);
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/// Compute the set of registers that need to be preserved and forwarded to
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/// any musttail calls.
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void analyzeMustTailForwardedRegisters(
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SmallVectorImpl<ForwardedRegister> &Forwards, ArrayRef<MVT> RegParmTypes,
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CCAssignFn Fn);
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private:
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/// MarkAllocated - Mark a register and all of its aliases as allocated.
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void MarkAllocated(unsigned Reg);
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@ -14,9 +14,11 @@
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/SaveAndRestore.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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@ -178,3 +180,57 @@ void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) {
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llvm_unreachable(nullptr);
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}
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}
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void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs,
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MVT VT, CCAssignFn Fn) {
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unsigned SavedStackOffset = StackOffset;
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unsigned NumLocs = Locs.size();
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// Allocate something of this value type repeatedly with just the inreg flag
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// set until we get assigned a location in memory.
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ISD::ArgFlagsTy Flags;
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Flags.setInReg();
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bool HaveRegParm = true;
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while (HaveRegParm) {
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if (Fn(0, VT, VT, CCValAssign::Full, Flags, *this)) {
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#ifndef NDEBUG
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dbgs() << "Call has unhandled type " << EVT(VT).getEVTString()
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<< " while computing remaining regparms\n";
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#endif
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llvm_unreachable(nullptr);
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}
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HaveRegParm = Locs.back().isRegLoc();
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}
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// Copy all the registers from the value locations we added.
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assert(NumLocs < Locs.size() && "CC assignment failed to add location");
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for (unsigned I = NumLocs, E = Locs.size(); I != E; ++I)
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if (Locs[I].isRegLoc())
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Regs.push_back(MCPhysReg(Locs[I].getLocReg()));
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// Clear the assigned values and stack memory. We leave the registers marked
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// as allocated so that future queries don't return the same registers, i.e.
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// when i64 and f64 are both passed in GPRs.
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StackOffset = SavedStackOffset;
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Locs.resize(NumLocs);
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}
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void CCState::analyzeMustTailForwardedRegisters(
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SmallVectorImpl<ForwardedRegister> &Forwards, ArrayRef<MVT> RegParmTypes,
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CCAssignFn Fn) {
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// Oftentimes calling conventions will not user register parameters for
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// variadic functions, so we need to assume we're not variadic so that we get
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// all the registers that might be used in a non-variadic call.
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SaveAndRestore<bool> SavedVarArg(IsVarArg, false);
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for (MVT RegVT : RegParmTypes) {
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SmallVector<MCPhysReg, 8> RemainingRegs;
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getRemainingRegParmsForType(RemainingRegs, RegVT, Fn);
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const TargetLowering *TL = MF.getSubtarget().getTargetLowering();
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const TargetRegisterClass *RC = TL->getRegClassFor(RegVT);
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for (MCPhysReg PReg : RemainingRegs) {
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unsigned VReg = MF.addLiveIn(PReg, RC);
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Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT));
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}
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}
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}
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@ -2549,11 +2549,19 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
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MFI->CreateFixedObject(1, StackSize, true));
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}
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// Figure out if XMM registers are in use.
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bool HaveXMMArgs = Is64Bit && !IsWin64;
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bool NoImplicitFloatOps = Fn->getAttributes().hasAttribute(
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AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
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assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
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"SSE register cannot be used when SSE is disabled!");
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if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
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!Subtarget->hasSSE1())
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HaveXMMArgs = false;
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// 64-bit calling conventions support varargs and register parameters, so we
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// have to do extra work to spill them in the prologue or forward them to
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// musttail calls.
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if (Is64Bit && isVarArg &&
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(MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
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// have to do extra work to spill them in the prologue.
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if (Is64Bit && isVarArg && MFI->hasVAStart()) {
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// Find the first unallocated argument registers.
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ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
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ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
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@ -2583,90 +2591,99 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
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}
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}
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// Store them to the va_list returned by va_start.
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if (MFI->hasVAStart()) {
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if (IsWin64) {
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const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
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// Get to the caller-allocated home save location. Add 8 to account
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// for the return address.
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int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
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FuncInfo->setRegSaveFrameIndex(
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if (IsWin64) {
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const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
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// Get to the caller-allocated home save location. Add 8 to account
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// for the return address.
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int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
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FuncInfo->setRegSaveFrameIndex(
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MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
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// Fixup to set vararg frame on shadow area (4 x i64).
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if (NumIntRegs < 4)
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FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
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} else {
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// For X86-64, if there are vararg parameters that are passed via
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// registers, then we must store them to their spots on the stack so
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// they may be loaded by deferencing the result of va_next.
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FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
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FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
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FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
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ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
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}
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// Store the integer parameter registers.
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SmallVector<SDValue, 8> MemOps;
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SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
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getPointerTy());
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unsigned Offset = FuncInfo->getVarArgsGPOffset();
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for (SDValue Val : LiveGPRs) {
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SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
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DAG.getIntPtrConstant(Offset));
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SDValue Store =
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DAG.getStore(Val.getValue(1), dl, Val, FIN,
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MachinePointerInfo::getFixedStack(
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FuncInfo->getRegSaveFrameIndex(), Offset),
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false, false, 0);
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MemOps.push_back(Store);
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Offset += 8;
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}
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if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
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// Now store the XMM (fp + vector) parameter registers.
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SmallVector<SDValue, 12> SaveXMMOps;
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SaveXMMOps.push_back(Chain);
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SaveXMMOps.push_back(ALVal);
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SaveXMMOps.push_back(DAG.getIntPtrConstant(
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FuncInfo->getRegSaveFrameIndex()));
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SaveXMMOps.push_back(DAG.getIntPtrConstant(
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FuncInfo->getVarArgsFPOffset()));
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SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
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LiveXMMRegs.end());
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MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
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MVT::Other, SaveXMMOps));
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}
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if (!MemOps.empty())
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Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
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// Fixup to set vararg frame on shadow area (4 x i64).
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if (NumIntRegs < 4)
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FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
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} else {
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// Add all GPRs, al, and XMMs to the list of forwards. We will add then
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// to the liveout set on a musttail call.
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assert(MFI->hasMustTailInVarArgFunc());
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auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
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typedef X86MachineFunctionInfo::Forward Forward;
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// For X86-64, if there are vararg parameters that are passed via
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// registers, then we must store them to their spots on the stack so
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// they may be loaded by deferencing the result of va_next.
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FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
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FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
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FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
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ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
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}
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for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
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unsigned VReg =
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MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
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Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
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Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
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}
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// Store the integer parameter registers.
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SmallVector<SDValue, 8> MemOps;
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SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
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getPointerTy());
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unsigned Offset = FuncInfo->getVarArgsGPOffset();
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for (SDValue Val : LiveGPRs) {
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SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
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DAG.getIntPtrConstant(Offset));
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SDValue Store =
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DAG.getStore(Val.getValue(1), dl, Val, FIN,
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MachinePointerInfo::getFixedStack(
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FuncInfo->getRegSaveFrameIndex(), Offset),
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false, false, 0);
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MemOps.push_back(Store);
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Offset += 8;
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}
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if (!ArgXMMs.empty()) {
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unsigned ALVReg =
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MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
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Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
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Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
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if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
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// Now store the XMM (fp + vector) parameter registers.
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SmallVector<SDValue, 12> SaveXMMOps;
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SaveXMMOps.push_back(Chain);
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SaveXMMOps.push_back(ALVal);
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SaveXMMOps.push_back(DAG.getIntPtrConstant(
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FuncInfo->getRegSaveFrameIndex()));
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SaveXMMOps.push_back(DAG.getIntPtrConstant(
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FuncInfo->getVarArgsFPOffset()));
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SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
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LiveXMMRegs.end());
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MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
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MVT::Other, SaveXMMOps));
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}
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for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
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unsigned VReg =
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MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
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Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
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Forwards.push_back(
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Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
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}
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}
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if (!MemOps.empty())
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Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
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}
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if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
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// Find the largest legal vector type.
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MVT VecVT = MVT::Other;
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// FIXME: Only some x86_32 calling conventions support AVX512.
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if (Subtarget->hasAVX512() &&
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(Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
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CallConv == CallingConv::Intel_OCL_BI)))
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VecVT = MVT::v16f32;
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else if (Subtarget->hasAVX())
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VecVT = MVT::v8f32;
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else if (Subtarget->hasSSE2())
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VecVT = MVT::v4f32;
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// We forward some GPRs and some vector types.
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SmallVector<MVT, 2> RegParmTypes;
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MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
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RegParmTypes.push_back(IntVT);
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if (VecVT != MVT::Other)
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RegParmTypes.push_back(VecVT);
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// Compute the set of forwarded registers. The rest are scratch.
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SmallVectorImpl<ForwardedRegister> &Forwards =
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FuncInfo->getForwardedMustTailRegParms();
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CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
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// Conservatively forward AL on x86_64, since it might be used for varargs.
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if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
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unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
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Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
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}
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// Copy all forwards from physical to virtual registers.
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for (ForwardedRegister &F : Forwards) {
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// FIXME: Can we use a less constrained schedule?
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SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
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F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
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Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
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}
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}
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@ -2986,7 +3003,7 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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DAG.getConstant(NumXMMRegs, MVT::i8)));
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}
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if (Is64Bit && isVarArg && IsMustTail) {
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if (isVarArg && IsMustTail) {
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const auto &Forwards = X86Info->getForwardedMustTailRegParms();
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for (const auto &F : Forwards) {
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SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
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@ -14,6 +14,7 @@
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#ifndef LLVM_LIB_TARGET_X86_X86MACHINEFUNCTIONINFO_H
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#define LLVM_LIB_TARGET_X86_X86MACHINEFUNCTIONINFO_H
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineValueType.h"
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#include <vector>
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@ -77,21 +78,10 @@ class X86MachineFunctionInfo : public MachineFunctionInfo {
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/// NumLocalDynamics - Number of local-dynamic TLS accesses.
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unsigned NumLocalDynamics;
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public:
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/// Describes a register that needs to be forwarded from the prologue to a
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/// musttail call.
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struct Forward {
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Forward(unsigned VReg, MCPhysReg PReg, MVT VT)
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: VReg(VReg), PReg(PReg), VT(VT) {}
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unsigned VReg;
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MCPhysReg PReg;
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MVT VT;
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};
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private:
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/// ForwardedMustTailRegParms - A list of virtual and physical registers
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/// that must be forwarded to every musttail call.
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std::vector<Forward> ForwardedMustTailRegParms;
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SmallVector<ForwardedRegister, 1> ForwardedMustTailRegParms;
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public:
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X86MachineFunctionInfo() : ForceFramePointer(false),
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@ -168,7 +158,7 @@ public:
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unsigned getNumLocalDynamicTLSAccesses() const { return NumLocalDynamics; }
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void incNumLocalDynamicTLSAccesses() { ++NumLocalDynamics; }
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std::vector<Forward> &getForwardedMustTailRegParms() {
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SmallVectorImpl<ForwardedRegister> &getForwardedMustTailRegParms() {
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return ForwardedMustTailRegParms;
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}
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};
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109
test/CodeGen/X86/musttail-fastcall.ll
Normal file
109
test/CodeGen/X86/musttail-fastcall.ll
Normal file
@ -0,0 +1,109 @@
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; RUN: llc < %s -mtriple=i686-pc-win32 -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE2
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; RUN: llc < %s -mtriple=i686-pc-win32 -mattr=+sse2,+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
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; RUN: llc < %s -mtriple=i686-pc-win32 -mattr=+sse2,+avx,+avx512f | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512
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; While we don't support varargs with fastcall, we do support forwarding.
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@asdf = internal constant [4 x i8] c"asdf"
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declare void @puts(i8*)
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define i32 @call_fast_thunk() {
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%r = call x86_fastcallcc i32 (...)* @fast_thunk(i32 inreg 1, i32 inreg 2, i32 3)
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ret i32 %r
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}
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define x86_fastcallcc i32 @fast_thunk(...) {
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call void @puts(i8* getelementptr ([4 x i8]* @asdf, i32 0, i32 0))
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%r = musttail call x86_fastcallcc i32 (...)* bitcast (i32 (i32, i32, i32)* @fast_target to i32 (...)*) (...)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
; Check that we spill and fill around the call to puts.
|
||||
|
||||
; CHECK-LABEL: @fast_thunk@0:
|
||||
; CHECK-DAG: movl %ecx, {{.*}}
|
||||
; CHECK-DAG: movl %edx, {{.*}}
|
||||
; CHECK: calll _puts
|
||||
; CHECK-DAG: movl {{.*}}, %ecx
|
||||
; CHECK-DAG: movl {{.*}}, %edx
|
||||
; CHECK: jmp @fast_target@12
|
||||
|
||||
define x86_fastcallcc i32 @fast_target(i32 inreg %a, i32 inreg %b, i32 %c) {
|
||||
%a0 = add i32 %a, %b
|
||||
%a1 = add i32 %a0, %c
|
||||
ret i32 %a1
|
||||
}
|
||||
|
||||
; Repeat the test for vectorcall, which has XMM registers.
|
||||
|
||||
define i32 @call_vector_thunk() {
|
||||
%r = call x86_vectorcallcc i32 (...)* @vector_thunk(i32 inreg 1, i32 inreg 2, i32 3)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define x86_vectorcallcc i32 @vector_thunk(...) {
|
||||
call void @puts(i8* getelementptr ([4 x i8]* @asdf, i32 0, i32 0))
|
||||
%r = musttail call x86_vectorcallcc i32 (...)* bitcast (i32 (i32, i32, i32)* @vector_target to i32 (...)*) (...)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
; Check that we spill and fill SSE registers around the call to puts.
|
||||
|
||||
; CHECK-LABEL: vector_thunk@@0:
|
||||
; CHECK-DAG: movl %ecx, {{.*}}
|
||||
; CHECK-DAG: movl %edx, {{.*}}
|
||||
|
||||
; SSE2-DAG: movups %xmm0, {{.*}}
|
||||
; SSE2-DAG: movups %xmm1, {{.*}}
|
||||
; SSE2-DAG: movups %xmm2, {{.*}}
|
||||
; SSE2-DAG: movups %xmm3, {{.*}}
|
||||
; SSE2-DAG: movups %xmm4, {{.*}}
|
||||
; SSE2-DAG: movups %xmm5, {{.*}}
|
||||
|
||||
; AVX-DAG: vmovups %ymm0, {{.*}}
|
||||
; AVX-DAG: vmovups %ymm1, {{.*}}
|
||||
; AVX-DAG: vmovups %ymm2, {{.*}}
|
||||
; AVX-DAG: vmovups %ymm3, {{.*}}
|
||||
; AVX-DAG: vmovups %ymm4, {{.*}}
|
||||
; AVX-DAG: vmovups %ymm5, {{.*}}
|
||||
|
||||
; AVX512-DAG: vmovups %zmm0, {{.*}}
|
||||
; AVX512-DAG: vmovups %zmm1, {{.*}}
|
||||
; AVX512-DAG: vmovups %zmm2, {{.*}}
|
||||
; AVX512-DAG: vmovups %zmm3, {{.*}}
|
||||
; AVX512-DAG: vmovups %zmm4, {{.*}}
|
||||
; AVX512-DAG: vmovups %zmm5, {{.*}}
|
||||
|
||||
; CHECK: calll _puts
|
||||
|
||||
; SSE2-DAG: movups {{.*}}, %xmm0
|
||||
; SSE2-DAG: movups {{.*}}, %xmm1
|
||||
; SSE2-DAG: movups {{.*}}, %xmm2
|
||||
; SSE2-DAG: movups {{.*}}, %xmm3
|
||||
; SSE2-DAG: movups {{.*}}, %xmm4
|
||||
; SSE2-DAG: movups {{.*}}, %xmm5
|
||||
|
||||
; AVX-DAG: vmovups {{.*}}, %ymm0
|
||||
; AVX-DAG: vmovups {{.*}}, %ymm1
|
||||
; AVX-DAG: vmovups {{.*}}, %ymm2
|
||||
; AVX-DAG: vmovups {{.*}}, %ymm3
|
||||
; AVX-DAG: vmovups {{.*}}, %ymm4
|
||||
; AVX-DAG: vmovups {{.*}}, %ymm5
|
||||
|
||||
; AVX512-DAG: vmovups {{.*}}, %zmm0
|
||||
; AVX512-DAG: vmovups {{.*}}, %zmm1
|
||||
; AVX512-DAG: vmovups {{.*}}, %zmm2
|
||||
; AVX512-DAG: vmovups {{.*}}, %zmm3
|
||||
; AVX512-DAG: vmovups {{.*}}, %zmm4
|
||||
; AVX512-DAG: vmovups {{.*}}, %zmm5
|
||||
|
||||
; CHECK-DAG: movl {{.*}}, %ecx
|
||||
; CHECK-DAG: movl {{.*}}, %edx
|
||||
; CHECK: jmp vector_target@@12
|
||||
|
||||
define x86_vectorcallcc i32 @vector_target(i32 inreg %a, i32 inreg %b, i32 %c) {
|
||||
%a0 = add i32 %a, %b
|
||||
%a1 = add i32 %a0, %c
|
||||
ret i32 %a1
|
||||
}
|
||||
@ -5,9 +5,16 @@
|
||||
; pack. Doing a normal call will clobber all argument registers, and we will
|
||||
; spill around it. A simple adjustment should not require any XMM spills.
|
||||
|
||||
declare void @llvm.va_start(i8*) nounwind
|
||||
|
||||
declare void(i8*, ...)* @get_f(i8* %this)
|
||||
|
||||
define void @f_thunk(i8* %this, ...) {
|
||||
; Use va_start so that we exercise the combination.
|
||||
%ap = alloca [4 x i8*], align 16
|
||||
%ap_i8 = bitcast [4 x i8*]* %ap to i8*
|
||||
call void @llvm.va_start(i8* %ap_i8)
|
||||
|
||||
%fptr = call void(i8*, ...)*(i8*)* @get_f(i8* %this)
|
||||
musttail call void (i8*, ...)* %fptr(i8* %this, ...)
|
||||
ret void
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user