6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-13 04:38:24 +00:00
Code Issues Projects Releases Wiki Activity

Remove xs1a subtarget. xs1a is a preproduction device used in

Browse Source 
early development boards which is no longer supported in the
XMOS toolchain.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83381 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne
2009-10-06 16:01:09 +00:00
parent acfbb92824
commit 34bee6da7a
7 changed files with 45 additions and 98 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
lib/Target/XCore/XCore.td
View File

@ -33,10 +33,6 @@ def XCoreInstrInfo : InstrInfo {
// XCore Subtarget features. // XCore Subtarget features.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def FeatureXS1A
: SubtargetFeature<"xs1a", "IsXS1A", "true",
"Enable XS1A instructions">;
def FeatureXS1B def FeatureXS1B
: SubtargetFeature<"xs1b", "IsXS1B", "true", : SubtargetFeature<"xs1b", "IsXS1B", "true",
"Enable XS1B instructions">; "Enable XS1B instructions">;
@ -48,8 +44,7 @@ def FeatureXS1B
class Proc<string Name, list<SubtargetFeature> Features> class Proc<string Name, list<SubtargetFeature> Features>
: Processor<Name, NoItineraries, Features>; : Processor<Name, NoItineraries, Features>;
def : Proc<"generic", [FeatureXS1A]>; def : Proc<"generic", [FeatureXS1B]>;
def : Proc<"xs1a-generic", [FeatureXS1A]>;
def : Proc<"xs1b-generic", [FeatureXS1B]>; def : Proc<"xs1b-generic", [FeatureXS1B]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

41
lib/Target/XCore/XCoreISelDAGToDAG.cpp
View File

@ -186,17 +186,14 @@ SDNode *XCoreDAGToDAGISel::Select(SDValue Op) {
} }
case ISD::SMUL_LOHI: { case ISD::SMUL_LOHI: {
// FIXME fold addition into the macc instruction // FIXME fold addition into the macc instruction
if (!Subtarget.isXS1A()) { SDValue Zero(CurDAG->getMachineNode(XCore::LDC_ru6, dl, MVT::i32,
SDValue Zero(CurDAG->getMachineNode(XCore::LDC_ru6, dl, MVT::i32, CurDAG->getTargetConstant(0, MVT::i32)), 0);
CurDAG->getTargetConstant(0, MVT::i32)), 0); SDValue Ops[] = { Zero, Zero, Op.getOperand(0), Op.getOperand(1) };
SDValue Ops[] = { Zero, Zero, Op.getOperand(0), Op.getOperand(1) }; SDNode *ResNode = CurDAG->getMachineNode(XCore::MACCS_l4r, dl,
SDNode *ResNode = CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32, Ops, 4);
MVT::i32, MVT::i32, Ops, 4); ReplaceUses(SDValue(N, 0), SDValue(ResNode, 1));
ReplaceUses(SDValue(N, 0), SDValue(ResNode, 1)); ReplaceUses(SDValue(N, 1), SDValue(ResNode, 0));
ReplaceUses(SDValue(N, 1), SDValue(ResNode, 0)); return NULL;
return NULL;
}
break;
} }
case ISD::UMUL_LOHI: { case ISD::UMUL_LOHI: {
// FIXME fold addition into the macc / lmul instruction // FIXME fold addition into the macc / lmul instruction
@ -211,22 +208,16 @@ SDNode *XCoreDAGToDAGISel::Select(SDValue Op) {
return NULL; return NULL;
} }
case XCoreISD::LADD: { case XCoreISD::LADD: {
if (!Subtarget.isXS1A()) { SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), Op.getOperand(2) };
Op.getOperand(2) }; return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32,
return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32, Ops, 3);
Ops, 3);
}
break;
} }
case XCoreISD::LSUB: { case XCoreISD::LSUB: {
if (!Subtarget.isXS1A()) { SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), Op.getOperand(2) };
Op.getOperand(2) }; return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32,
return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32, Ops, 3);
Ops, 3);
}
break;
} }
// Other cases are autogenerated. // Other cases are autogenerated.
} }

52
lib/Target/XCore/XCoreISelLowering.cpp
View File

@ -89,13 +89,8 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
// 64bit // 64bit
if (!Subtarget.isXS1A()) { setOperationAction(ISD::ADD, MVT::i64, Custom);
setOperationAction(ISD::ADD, MVT::i64, Custom); setOperationAction(ISD::SUB, MVT::i64, Custom);
setOperationAction(ISD::SUB, MVT::i64, Custom);
}
if (Subtarget.isXS1A()) {
setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
}
setOperationAction(ISD::MULHS, MVT::i32, Expand); setOperationAction(ISD::MULHS, MVT::i32, Expand);
setOperationAction(ISD::MULHU, MVT::i32, Expand); setOperationAction(ISD::MULHU, MVT::i32, Expand);
setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
@ -221,17 +216,16 @@ getGlobalAddressWrapper(SDValue GA, GlobalValue *GV, SelectionDAG &DAG)
DebugLoc dl = GA.getDebugLoc(); DebugLoc dl = GA.getDebugLoc();
if (isa<Function>(GV)) { if (isa<Function>(GV)) {
return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA);
} else if (!Subtarget.isXS1A()) { }
const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
if (!GVar) { if (!GVar) {
// If GV is an alias then use the aliasee to determine constness // If GV is an alias then use the aliasee to determine constness
if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal()); GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal());
} }
bool isConst = GVar && GVar->isConstant(); bool isConst = GVar && GVar->isConstant();
if (isConst) { if (isConst) {
return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
}
} }
return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA);
} }
@ -297,21 +291,16 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG)
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
// FIXME there isn't really debug info here // FIXME there isn't really debug info here
DebugLoc dl = CP->getDebugLoc(); DebugLoc dl = CP->getDebugLoc();
if (Subtarget.isXS1A()) { EVT PtrVT = Op.getValueType();
llvm_unreachable("Lowering of constant pool unimplemented"); SDValue Res;
return SDValue(); if (CP->isMachineConstantPoolEntry()) {
Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
CP->getAlignment());
} else { } else {
EVT PtrVT = Op.getValueType(); Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
SDValue Res; CP->getAlignment());
if (CP->isMachineConstantPoolEntry()) {
Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
CP->getAlignment());
} else {
Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
CP->getAlignment());
}
return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res);
} }
return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res);
} }
SDValue XCoreTargetLowering:: SDValue XCoreTargetLowering::
@ -524,7 +513,6 @@ ExpandADDSUB(SDNode *N, SelectionDAG &DAG)
assert(N->getValueType(0) == MVT::i64 && assert(N->getValueType(0) == MVT::i64 &&
(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
"Unknown operand to lower!"); "Unknown operand to lower!");
assert(!Subtarget.isXS1A() && "Cannot custom lower ADD/SUB on xs1a");
DebugLoc dl = N->getDebugLoc(); DebugLoc dl = N->getDebugLoc();
// Extract components // Extract components

17
lib/Target/XCore/XCoreInstrInfo.td
View File

@ -26,10 +26,6 @@ include "XCoreInstrFormats.td"
// Feature predicates. // Feature predicates.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// HasXS1A - This predicate is true when the target processor supports XS1A
// instructions.
def HasXS1A : Predicate<"Subtarget.isXS1A()">;
// HasXS1B - This predicate is true when the target processor supports XS1B // HasXS1B - This predicate is true when the target processor supports XS1B
// instructions. // instructions.
def HasXS1B : Predicate<"Subtarget.isXS1B()">; def HasXS1B : Predicate<"Subtarget.isXS1B()">;
@ -142,9 +138,6 @@ def immU20 : PatLeaf<(imm), [{
return (uint32_t)N->getZExtValue() < (1 << 20); return (uint32_t)N->getZExtValue() < (1 << 20);
}]>; }]>;
// FIXME check subtarget. Currently we check if the immediate
// is in the common subset of legal immediate values for both
// XS1A and XS1B.
def immMskBitp : PatLeaf<(imm), [{ def immMskBitp : PatLeaf<(imm), [{
uint32_t value = (uint32_t)N->getZExtValue(); uint32_t value = (uint32_t)N->getZExtValue();
if (!isMask_32(value)) { if (!isMask_32(value)) {
@ -157,9 +150,6 @@ def immMskBitp : PatLeaf<(imm), [{
|| msksize == 32; || msksize == 32;
}]>; }]>;
// FIXME check subtarget. Currently we check if the immediate
// is in the common subset of legal immediate values for both
// XS1A and XS1B.
def immBitp : PatLeaf<(imm), [{ def immBitp : PatLeaf<(imm), [{
uint32_t value = (uint32_t)N->getZExtValue(); uint32_t value = (uint32_t)N->getZExtValue();
return (value >= 1 && value <= 8) return (value >= 1 && value <= 8)
@ -524,13 +514,6 @@ def LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2),
"lmul $dst1, $dst2, $src1, $src2, $src3, $src4", "lmul $dst1, $dst2, $src1, $src2, $src3, $src4",
[]>; []>;
let Predicates = [HasXS1A] in
def MACC_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2),
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
GRRegs:$src4),
"macc $dst1, $dst2, $src1, $src2, $src3, $src4",
[]>;
// Register - U6 // Register - U6
//let Uses = [DP] in ... //let Uses = [DP] in ...

3
lib/Target/XCore/XCoreSubtarget.cpp
View File

@ -17,8 +17,7 @@
using namespace llvm; using namespace llvm;
XCoreSubtarget::XCoreSubtarget(const std::string &TT, const std::string &FS) XCoreSubtarget::XCoreSubtarget(const std::string &TT, const std::string &FS)
: IsXS1A(false), : IsXS1B(false)
IsXS1B(false)
{ {
std::string CPU = "xs1b-generic"; std::string CPU = "xs1b-generic";

2
lib/Target/XCore/XCoreSubtarget.h
View File

@ -22,7 +22,6 @@
namespace llvm { namespace llvm {
class XCoreSubtarget : public TargetSubtarget { class XCoreSubtarget : public TargetSubtarget {
bool IsXS1A;
bool IsXS1B; bool IsXS1B;
public: public:
@ -31,7 +30,6 @@ public:
/// ///
XCoreSubtarget(const std::string &TT, const std::string &FS); XCoreSubtarget(const std::string &TT, const std::string &FS);
bool isXS1A() const { return IsXS1A; }
bool isXS1B() const { return IsXS1B; } bool isXS1B() const { return IsXS1B; }
/// ParseSubtargetFeatures - Parses features string setting specified /// ParseSubtargetFeatures - Parses features string setting specified

21
lib/Target/XCore/XCoreTargetObjectFile.cpp
View File

@ -52,20 +52,13 @@ void XCoreTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM){
// and can be placed in the standard data / bss sections. // and can be placed in the standard data / bss sections.
TLSDataSection = DataSection; TLSDataSection = DataSection;
TLSBSSSection = BSSSection; TLSBSSSection = BSSSection;
if (TM.getSubtarget<XCoreSubtarget>().isXS1A()) ReadOnlySection =
ReadOnlySection = // FIXME: Why is this a writable section for XS1A? MCSectionXCore::Create(".cp.rodata", MCSectionELF::SHT_PROGBITS,
MCSectionXCore::Create(".dp.rodata", MCSectionELF::SHT_PROGBITS, MCSectionELF::SHF_ALLOC |
MCSectionELF::SHF_ALLOC | MCSectionELF::SHF_WRITE | MCSectionXCore::SHF_CP_SECTION,
MCSectionXCore::SHF_DP_SECTION, SectionKind::getReadOnlyWithRel(), false,
SectionKind::getDataRel(), false, getContext()); getContext());
else
ReadOnlySection =
MCSectionXCore::Create(".cp.rodata", MCSectionELF::SHT_PROGBITS,
MCSectionELF::SHF_ALLOC |
MCSectionXCore::SHF_CP_SECTION,
SectionKind::getReadOnlyWithRel(), false,
getContext());
// Dynamic linking is not supported. Data with relocations is placed in the // Dynamic linking is not supported. Data with relocations is placed in the
// same section as data without relocations. // same section as data without relocations.