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Teach coalescer about earlyclobber bits.

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Check bits for preferred register.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56384 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen
2008-09-20 02:03:04 +00:00
parent 5e8d9def77
commit 34d8f7559c
2 changed files with 17 additions and 2 deletions
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7
lib/CodeGen/RegAllocLinearScan.cpp
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@@ -1122,9 +1122,12 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
unsigned FreeRegInactiveCount = 0;
// If copy coalescer has assigned a "preferred" register, check if it's
// available first.
// available first. Coalescer can create new earlyclobber interferences,
// so we need to check that.
if (cur->preference) {
if (prt_->isRegAvail(cur->preference) && RC->contains(cur->preference)) {
if (prt_->isRegAvail(cur->preference) &&
RC->contains(cur->preference) &&
noEarlyClobberConflict(cur, cur->preference)) {
DOUT << "\t\tassigned the preferred register: "
<< tri_->getName(cur->preference) << "\n";
return cur->preference;