6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-01 00:33:09 +00:00
Code Issues Projects Releases Wiki Activity

[mips] Try to fix the test/ExecutionEngine tests on a MIPS host.

Browse Source 
Fix a dangerous default case that caused MipsCodeEmitter to discard pseudo
instructions it didn't recognize. It will now call llvm_unreachable() for
unrecognized pseudo's and explicitly handles PseudoReturn, PseudoReturn64,
PseudoIndirectBranch, PseudoIndirectBranch64, CFI_INSTRUCTION, IMPLICIT_DEF,
and KILL.

There may be other pseudos that need handling but this was enough for the
ExecutionEngine tests to pass on my test system.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213513 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2014-07-21 12:25:34 +00:00
parent 8ecdc6d34f
commit 34e658840e
1 changed files with 49 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

51
lib/Target/Mips/MipsCodeEmitter.cpp
View File

@ -130,6 +130,9 @@ private:
void expandACCInstr(MachineBasicBlock::instr_iterator MI,
MachineBasicBlock &MBB, unsigned Opc) const;
void expandPseudoIndirectBranch(MachineBasicBlock::instr_iterator MI,
MachineBasicBlock &MBB) const;
/// \brief Expand pseudo instruction. Return true if MI was expanded.
bool expandPseudos(MachineBasicBlock::instr_iterator &MI,
MachineBasicBlock &MBB) const;
@ -373,9 +376,44 @@ void MipsCodeEmitter::expandACCInstr(MachineBasicBlock::instr_iterator MI,
.addReg(MI->getOperand(1).getReg()).addReg(MI->getOperand(2).getReg());
}
void MipsCodeEmitter::expandPseudoIndirectBranch(
MachineBasicBlock::instr_iterator MI, MachineBasicBlock &MBB) const {
// This logic is duplicated from MipsAsmPrinter::emitPseudoIndirectBranch()
bool HasLinkReg = false;
unsigned Opcode = 0;
if (Subtarget->hasMips64r6()) {
// MIPS64r6 should use (JALR64 ZERO_64, $rs)
Opcode = Mips::JALR64;
HasLinkReg = true;
} else if (Subtarget->hasMips32r6()) {
// MIPS32r6 should use (JALR ZERO, $rs)
Opcode = Mips::JALR;
HasLinkReg = true;
} else if (Subtarget->inMicroMipsMode())
// microMIPS should use (JR_MM $rs)
Opcode = Mips::JR_MM;
else {
// Everything else should use (JR $rs)
Opcode = Mips::JR;
}
auto MIB = BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Opcode));
if (HasLinkReg) {
unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
MIB.addReg(ZeroReg);
}
MIB.addReg(MI->getOperand(0).getReg());
}
bool MipsCodeEmitter::expandPseudos(MachineBasicBlock::instr_iterator &MI,
MachineBasicBlock &MBB) const {
switch (MI->getOpcode()) {
default:
llvm_unreachable("Unhandled pseudo");
return false;
case Mips::NOP:
BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::SLL), Mips::ZERO)
.addReg(Mips::ZERO).addImm(0);
@ -416,8 +454,17 @@ bool MipsCodeEmitter::expandPseudos(MachineBasicBlock::instr_iterator &MI,
case Mips::PseudoMSUBU:
expandACCInstr(MI, MBB, Mips::MSUBU);
break;
default:
return false;
case Mips::PseudoReturn:
case Mips::PseudoReturn64:
case Mips::PseudoIndirectBranch:
case Mips::PseudoIndirectBranch64:
expandPseudoIndirectBranch(MI, MBB);
break;
case TargetOpcode::CFI_INSTRUCTION:
case TargetOpcode::IMPLICIT_DEF:
case TargetOpcode::KILL:
// Do nothing
return false;
}
(MI--)->eraseFromBundle();