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Tighten operand checking on CPS instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137172 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2011-08-09 23:05:39 +00:00
parent 438f68df35
commit 35008c2f8d
4 changed files with 7 additions and 2 deletions
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2
lib/Target/ARM/ARMInstrInfo.td
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@ -1390,6 +1390,7 @@ class CPS<dag iops, string asm_ops>
let Inst{4-0} = mode; let Inst{4-0} = mode;
} }
let DecoderMethod = "DecodeCPSInstruction" in {
let M = 1 in let M = 1 in
def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
"$imod\t$iflags, $mode">; "$imod\t$iflags, $mode">;
@ -1398,6 +1399,7 @@ let mode = 0, M = 0 in
let imod = 0, iflags = 0, M = 1 in let imod = 0, iflags = 0, M = 1 in
def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
}
// Preload signals the memory system of possible future data/instruction access. // Preload signals the memory system of possible future data/instruction access.
// These are for disassembly only. // These are for disassembly only.

5
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -83,6 +83,8 @@ static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
const void *Decoder); const void *Decoder);
static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
@ -1139,6 +1141,9 @@ static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
unsigned iflags = fieldFromInstruction32(Insn, 6, 3); unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
unsigned mode = fieldFromInstruction32(Insn, 0, 5); unsigned mode = fieldFromInstruction32(Insn, 0, 5);
// imod == '01' --> UNPREDICTABLE
if (imod == 1) return false;
if (M && mode && imod && iflags) { if (M && mode && imod && iflags) {
Inst.setOpcode(ARM::CPS3p); Inst.setOpcode(ARM::CPS3p);
Inst.addOperand(MCOperand::CreateImm(imod)); Inst.addOperand(MCOperand::CreateImm(imod));

1
test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt
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@ -1,5 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# XFAIL: *
# invalid imod value (0b01) # invalid imod value (0b01)
0xc0 0x67 0x4 0xf1 0xc0 0x67 0x4 0xf1

1
test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt
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@ -1,5 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# XFAIL: *
# invalid (imod, M, iflags) combination # invalid (imod, M, iflags) combination
0x93 0x1c 0x02 0xf1 0x93 0x1c 0x02 0xf1