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Rename MachineInstrInfo -> TargetInstrInfo

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5272 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2003-01-14 22:00:31 +00:00
parent d640a6b4cf
commit 3501feab81
40 changed files with 109 additions and 500 deletions
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386
include/llvm/Target/MachineInstrInfo.h
View File

@ -1,386 +0,0 @@
//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
//
// This file describes the target machine instructions to the code generator.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_TARGET_MACHINEINSTRINFO_H
#define LLVM_TARGET_MACHINEINSTRINFO_H
#include "Support/DataTypes.h"
#include <vector>
class MachineInstr;
class TargetMachine;
class Value;
class Instruction;
class Constant;
class Function;
class MachineCodeForInstruction;
//---------------------------------------------------------------------------
// Data types used to define information about a single machine instruction
//---------------------------------------------------------------------------
typedef int MachineOpCode;
typedef unsigned InstrSchedClass;
const MachineOpCode INVALID_MACHINE_OPCODE = -1;
//---------------------------------------------------------------------------
// struct MachineInstrDescriptor:
// Predefined information about each machine instruction.
// Designed to initialized statically.
//
// class MachineInstructionInfo
// Interface to description of machine instructions
//
//---------------------------------------------------------------------------
const unsigned M_NOP_FLAG = 1 << 0;
const unsigned M_BRANCH_FLAG = 1 << 1;
const unsigned M_CALL_FLAG = 1 << 2;
const unsigned M_RET_FLAG = 1 << 3;
const unsigned M_ARITH_FLAG = 1 << 4;
const unsigned M_CC_FLAG = 1 << 6;
const unsigned M_LOGICAL_FLAG = 1 << 6;
const unsigned M_INT_FLAG = 1 << 7;
const unsigned M_FLOAT_FLAG = 1 << 8;
const unsigned M_CONDL_FLAG = 1 << 9;
const unsigned M_LOAD_FLAG = 1 << 10;
const unsigned M_PREFETCH_FLAG = 1 << 11;
const unsigned M_STORE_FLAG = 1 << 12;
const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction
// 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub
const unsigned M_2_ADDR_FLAG = 1 << 15;
// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
// block? Typically this is things like return and branch instructions.
// Various passes use this to insert code into the bottom of a basic block, but
// before control flow occurs.
const unsigned M_TERMINATOR_FLAG = 1 << 16;
struct TargetInstrDescriptor {
const char * Name; // Assembly language mnemonic for the opcode.
int numOperands; // Number of args; -1 if variable #args
int resultPos; // Position of the result; -1 if no result
unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0.
bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
// smallest -ve value is -(maxImmedConst+1).
unsigned numDelaySlots; // Number of delay slots after instruction
unsigned latency; // Latency in machine cycles
InstrSchedClass schedClass; // enum identifying instr sched class
unsigned Flags; // flags identifying machine instr class
unsigned TSFlags; // Target Specific Flag values
const unsigned *ImplicitUses; // Registers implicitly read by this instr
const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
};
typedef TargetInstrDescriptor MachineInstrDescriptor;
class TargetInstrInfo {
const TargetInstrDescriptor* desc; // raw array to allow static init'n
unsigned descSize; // number of entries in the desc array
unsigned numRealOpCodes; // number of non-dummy op codes
TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
public:
TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned descSize,
unsigned numRealOpCodes);
virtual ~TargetInstrInfo();
// Invariant: All instruction sets use opcode #0 as the PHI instruction and
// opcode #1 as the noop instruction.
enum {
PHI = 0, NOOP = 1
};
unsigned getNumRealOpCodes() const { return numRealOpCodes; }
unsigned getNumTotalOpCodes() const { return descSize; }
/// get - Return the machine instruction descriptor that corresponds to the
/// specified instruction opcode.
///
const TargetInstrDescriptor& get(MachineOpCode opCode) const {
assert(opCode >= 0 && opCode < (int)descSize);
return desc[opCode];
}
/// print - Print out the specified machine instruction in the appropriate
/// target specific assembly language. If this method is not overridden, the
/// default implementation uses the crummy machine independant printer.
///
virtual void print(const MachineInstr *MI, std::ostream &O,
const TargetMachine &TM) const;
const char *getName(MachineOpCode opCode) const {
return get(opCode).Name;
}
int getNumOperands(MachineOpCode opCode) const {
return get(opCode).numOperands;
}
int getResultPos(MachineOpCode opCode) const {
return get(opCode).resultPos;
}
unsigned getNumDelaySlots(MachineOpCode opCode) const {
return get(opCode).numDelaySlots;
}
InstrSchedClass getSchedClass(MachineOpCode opCode) const {
return get(opCode).schedClass;
}
//
// Query instruction class flags according to the machine-independent
// flags listed above.
//
bool isNop(MachineOpCode opCode) const {
return get(opCode).Flags & M_NOP_FLAG;
}
bool isBranch(MachineOpCode opCode) const {
return get(opCode).Flags & M_BRANCH_FLAG;
}
bool isCall(MachineOpCode opCode) const {
return get(opCode).Flags & M_CALL_FLAG;
}
bool isReturn(MachineOpCode opCode) const {
return get(opCode).Flags & M_RET_FLAG;
}
bool isControlFlow(MachineOpCode opCode) const {
return get(opCode).Flags & M_BRANCH_FLAG
|| get(opCode).Flags & M_CALL_FLAG
|| get(opCode).Flags & M_RET_FLAG;
}
bool isArith(MachineOpCode opCode) const {
return get(opCode).Flags & M_ARITH_FLAG;
}
bool isCCInstr(MachineOpCode opCode) const {
return get(opCode).Flags & M_CC_FLAG;
}
bool isLogical(MachineOpCode opCode) const {
return get(opCode).Flags & M_LOGICAL_FLAG;
}
bool isIntInstr(MachineOpCode opCode) const {
return get(opCode).Flags & M_INT_FLAG;
}
bool isFloatInstr(MachineOpCode opCode) const {
return get(opCode).Flags & M_FLOAT_FLAG;
}
bool isConditional(MachineOpCode opCode) const {
return get(opCode).Flags & M_CONDL_FLAG;
}
bool isLoad(MachineOpCode opCode) const {
return get(opCode).Flags & M_LOAD_FLAG;
}
bool isPrefetch(MachineOpCode opCode) const {
return get(opCode).Flags & M_PREFETCH_FLAG;
}
bool isLoadOrPrefetch(MachineOpCode opCode) const {
return get(opCode).Flags & M_LOAD_FLAG
|| get(opCode).Flags & M_PREFETCH_FLAG;
}
bool isStore(MachineOpCode opCode) const {
return get(opCode).Flags & M_STORE_FLAG;
}
bool isMemoryAccess(MachineOpCode opCode) const {
return get(opCode).Flags & M_LOAD_FLAG
|| get(opCode).Flags & M_PREFETCH_FLAG
|| get(opCode).Flags & M_STORE_FLAG;
}
bool isDummyPhiInstr(MachineOpCode opCode) const {
return get(opCode).Flags & M_DUMMY_PHI_FLAG;
}
bool isPseudoInstr(MachineOpCode opCode) const {
return get(opCode).Flags & M_PSEUDO_FLAG;
}
bool isTwoAddrInstr(MachineOpCode opCode) const {
return get(opCode).Flags & M_2_ADDR_FLAG;
}
bool isTerminatorInstr(unsigned Opcode) const {
return get(Opcode).Flags & M_TERMINATOR_FLAG;
}
// Check if an instruction can be issued before its operands are ready,
// or if a subsequent instruction that uses its result can be issued
// before the results are ready.
// Default to true since most instructions on many architectures allow this.
//
virtual bool hasOperandInterlock(MachineOpCode opCode) const {
return true;
}
virtual bool hasResultInterlock(MachineOpCode opCode) const {
return true;
}
//
// Latencies for individual instructions and instruction pairs
//
virtual int minLatency(MachineOpCode opCode) const {
return get(opCode).latency;
}
virtual int maxLatency(MachineOpCode opCode) const {
return get(opCode).latency;
}
//
// Which operand holds an immediate constant? Returns -1 if none
//
virtual int getImmedConstantPos(MachineOpCode opCode) const {
return -1; // immediate position is machine specific, so say -1 == "none"
}
// Check if the specified constant fits in the immediate field
// of this machine instruction
//
virtual bool constantFitsInImmedField(MachineOpCode opCode,
int64_t intValue) const;
// Return the largest +ve constant that can be held in the IMMMED field
// of this machine instruction.
// isSignExtended is set to true if the value is sign-extended before use
// (this is true for all immediate fields in SPARC instructions).
// Return 0 if the instruction has no IMMED field.
//
virtual uint64_t maxImmedConstant(MachineOpCode opCode,
bool &isSignExtended) const {
isSignExtended = get(opCode).immedIsSignExtended;
return get(opCode).maxImmedConst;
}
//-------------------------------------------------------------------------
// Queries about representation of LLVM quantities (e.g., constants)
//-------------------------------------------------------------------------
/// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded
/// from memory into a register, i.e., cannot be set bitwise in register and
/// cannot use immediate fields of instructions. Note that this only makes
/// sense for primitive types.
///
virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const;
// Test if this constant may not fit in the immediate field of the
// machine instructions (probably) generated for this instruction.
//
virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
const Instruction* I) const {
return true; // safe but very conservative
}
//-------------------------------------------------------------------------
// Code generation support for creating individual machine instructions
//
// WARNING: These methods are Sparc specific
//
//-------------------------------------------------------------------------
// Get certain common op codes for the current target. this and all the
// Create* methods below should be moved to a machine code generation class
//
virtual MachineOpCode getNOPOpCode() const { abort(); }
// Create an instruction sequence to put the constant `val' into
// the virtual register `dest'. `val' may be a Constant or a
// GlobalValue, viz., the constant address of a global variable or function.
// The generated instructions are returned in `mvec'.
// Any temp. registers (TmpInstruction) created are recorded in mcfi.
// Symbolic constants or constants that must be accessed from memory
// are added to the constant pool via MachineFunction::get(F).
//
virtual void CreateCodeToLoadConst(const TargetMachine& target,
Function* F,
Value* val,
Instruction* dest,
std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi) const {
abort();
}
// Create an instruction sequence to copy an integer value `val'
// to a floating point value `dest' by copying to memory and back.
// val must be an integral type. dest must be a Float or Double.
// The generated instructions are returned in `mvec'.
// Any temp. registers (TmpInstruction) created are recorded in mcfi.
// Any stack space required is allocated via mcff.
//
virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
Function* F,
Value* val,
Instruction* dest,
std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& MI) const {
abort();
}
// Similarly, create an instruction sequence to copy an FP value
// `val' to an integer value `dest' by copying to memory and back.
// The generated instructions are returned in `mvec'.
// Any temp. registers (TmpInstruction) created are recorded in mcfi.
// Any stack space required is allocated via mcff.
//
virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
Function* F,
Value* val,
Instruction* dest,
std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& MI) const {
abort();
}
// Create instruction(s) to copy src to dest, for arbitrary types
// The generated instructions are returned in `mvec'.
// Any temp. registers (TmpInstruction) created are recorded in mcfi.
// Any stack space required is allocated via mcff.
//
virtual void CreateCopyInstructionsByType(const TargetMachine& target,
Function* F,
Value* src,
Instruction* dest,
std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& MI) const {
abort();
}
// Create instruction sequence to produce a sign-extended register value
// from an arbitrary sized value (sized in bits, not bytes).
// The generated instructions are appended to `mvec'.
// Any temp. registers (TmpInstruction) created are recorded in mcfi.
// Any stack space required is allocated via mcff.
//
virtual void CreateSignExtensionInstructions(const TargetMachine& target,
Function* F,
Value* srcVal,
Value* destVal,
unsigned numLowBits,
std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& MI) const {
abort();
}
// Create instruction sequence to produce a zero-extended register value
// from an arbitrary sized value (sized in bits, not bytes).
// The generated instructions are appended to `mvec'.
// Any temp. registers (TmpInstruction) created are recorded in mcfi.
// Any stack space required is allocated via mcff.
//
virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
Function* F,
Value* srcVal,
Value* destVal,
unsigned srcSizeInBits,
std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi) const {
abort();
}
};
typedef TargetInstrInfo MachineInstrInfo;
#endif

19
include/llvm/Target/TargetInstrInfo.h
View File

@ -4,8 +4,8 @@
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_TARGET_MACHINEINSTRINFO_H
#define LLVM_TARGET_MACHINEINSTRINFO_H
#ifndef LLVM_TARGET_TARGETINSTRINFO_H
#define LLVM_TARGET_TARGETINSTRINFO_H
#include "Support/DataTypes.h"
#include <vector>
@ -29,14 +29,10 @@ const MachineOpCode INVALID_MACHINE_OPCODE = -1;
//---------------------------------------------------------------------------
// struct MachineInstrDescriptor:
// struct TargetInstrDescriptor:
// Predefined information about each machine instruction.
// Designed to initialized statically.
//
// class MachineInstructionInfo
// Interface to description of machine instructions
//
//---------------------------------------------------------------------------
//
const unsigned M_NOP_FLAG = 1 << 0;
const unsigned M_BRANCH_FLAG = 1 << 1;
@ -78,8 +74,11 @@ struct TargetInstrDescriptor {
const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
};
typedef TargetInstrDescriptor MachineInstrDescriptor;
//---------------------------------------------------------------------------
///
/// TargetInstrInfo - Interface to description of machine instructions
///
class TargetInstrInfo {
const TargetInstrDescriptor* desc; // raw array to allow static init'n
unsigned descSize; // number of entries in the desc array
@ -381,6 +380,4 @@ public:
}
};
typedef TargetInstrInfo MachineInstrInfo;
#endif

2
include/llvm/Target/TargetRegInfo.h
View File

@ -126,7 +126,7 @@ public:
// The following methods are used to generate "copy" machine instructions
// for an architecture. Currently they are used in TargetRegClass
// interface. However, they can be moved to MachineInstrInfo interface if
// interface. However, they can be moved to TargetInstrInfo interface if
// necessary.
//
// The function regTypeNeedsScratchReg() can be used to check whether a

6
include/llvm/Target/TargetSchedInfo.h
View File

@ -7,7 +7,7 @@
#ifndef LLVM_TARGET_TARGETSCHEDINFO_H
#define LLVM_TARGET_TARGETSCHEDINFO_H
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "Support/hash_map"
#include <string>
@ -211,7 +211,7 @@ public:
unsigned _numIssueDeltas);
/*dtor*/ virtual ~TargetSchedInfo() {}
inline const MachineInstrInfo& getInstrInfo() const {
inline const TargetInstrInfo& getInstrInfo() const {
return *mii;
}
@ -283,7 +283,7 @@ private:
protected:
unsigned numSchedClasses;
const MachineInstrInfo* mii;
const TargetInstrInfo* mii;
const InstrClassRUsage* classRUsages; // raw array by sclass
const InstrRUsageDelta* usageDeltas; // raw array [1:numUsageDeltas]
const InstrIssueDelta* issueDeltas; // raw array [1:numIssueDeltas]

12
lib/CodeGen/InstrSched/InstrScheduling.cpp
View File

@ -370,7 +370,7 @@ public:
// Simplify access to the machine instruction info
//----------------------------------------------------------------------
inline const MachineInstrInfo& getInstrInfo () const {
inline const TargetInstrInfo& getInstrInfo () const {
return schedInfo.getInstrInfo();
}
@ -630,7 +630,7 @@ AssignInstructionsToSlots(class SchedulingManager& S, unsigned maxIssue)
static void
RecordSchedule(MachineBasicBlock &MBB, const SchedulingManager& S)
{
const MachineInstrInfo& mii = S.schedInfo.getInstrInfo();
const TargetInstrInfo& mii = S.schedInfo.getInstrInfo();
#ifndef NDEBUG
// Lets make sure we didn't lose any instructions, except possibly
@ -1075,7 +1075,7 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
return false;
// don't put a load-use dependence in the delay slot of a branch
const MachineInstrInfo& mii = S.getInstrInfo();
const TargetInstrInfo& mii = S.getInstrInfo();
for (SchedGraphNode::const_iterator EI = node->beginInEdges();
EI != node->endInEdges(); ++EI)
@ -1143,7 +1143,7 @@ FindUsefulInstructionsForDelaySlots(SchedulingManager& S,
SchedGraphNode* brNode,
vector<SchedGraphNode*>& sdelayNodeVec)
{
const MachineInstrInfo& mii = S.getInstrInfo();
const TargetInstrInfo& mii = S.getInstrInfo();
unsigned ndelays =
mii.getNumDelaySlots(brNode->getOpCode());
@ -1207,7 +1207,7 @@ static void ReplaceNopsWithUsefulInstr(SchedulingManager& S,
SchedGraph* graph)
{
vector<SchedGraphNode*> nopNodeVec; // this will hold unused NOPs
const MachineInstrInfo& mii = S.getInstrInfo();
const TargetInstrInfo& mii = S.getInstrInfo();
const MachineInstr* brInstr = node->getMachineInstr();
unsigned ndelays= mii.getNumDelaySlots(brInstr->getOpCode());
assert(ndelays > 0 && "Unnecessary call to replace NOPs");
@ -1283,7 +1283,7 @@ static void
ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB,
SchedGraph *graph)
{
const MachineInstrInfo& mii = S.getInstrInfo();
const TargetInstrInfo& mii = S.getInstrInfo();
Instruction *termInstr = (Instruction*)MBB.getBasicBlock()->getTerminator();
MachineCodeForInstruction &termMvec=MachineCodeForInstruction::get(termInstr);

12
lib/CodeGen/InstrSched/SchedGraph.cpp
View File

@ -12,7 +12,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetRegInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Function.h"
#include "llvm/iOther.h"
#include "Support/StringExtras.h"
@ -325,7 +325,7 @@ void
SchedGraph::addCDEdges(const TerminatorInst* term,
const TargetMachine& target)
{
const MachineInstrInfo& mii = target.getInstrInfo();
const TargetInstrInfo& mii = target.getInstrInfo();
MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
// Find the first branch instr in the sequence of machine instrs for term
@ -434,7 +434,7 @@ void
SchedGraph::addMemEdges(const vector<SchedGraphNode*>& memNodeVec,
const TargetMachine& target)
{
const MachineInstrInfo& mii = target.getInstrInfo();
const TargetInstrInfo& mii = target.getInstrInfo();
// Instructions in memNodeVec are in execution order within the basic block,
// so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
@ -471,7 +471,7 @@ SchedGraph::addCallCCEdges(const vector<SchedGraphNode*>& memNodeVec,
MachineBasicBlock& bbMvec,
const TargetMachine& target)
{
const MachineInstrInfo& mii = target.getInstrInfo();
const TargetInstrInfo& mii = target.getInstrInfo();
vector<SchedGraphNode*> callNodeVec;
// Find the call instruction nodes and put them in a vector.
@ -675,7 +675,7 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
RegToRefVecMap& regToRefVecMap,
ValueToDefVecMap& valueToDefVecMap)
{
const MachineInstrInfo& mii = target.getInstrInfo();
const TargetInstrInfo& mii = target.getInstrInfo();
MachineOpCode opCode = node->getOpCode();
@ -732,7 +732,7 @@ SchedGraph::buildNodesForBB(const TargetMachine& target,
RegToRefVecMap& regToRefVecMap,
ValueToDefVecMap& valueToDefVecMap)
{
const MachineInstrInfo& mii = target.getInstrInfo();
const TargetInstrInfo& mii = target.getInstrInfo();
// Build graph nodes for each VM instruction and gather def/use info.
// Do both those together in a single pass over all machine instructions.

4
lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
View File

@ -14,7 +14,7 @@
#include "llvm/CodeGen/InstrForest.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegInfo.h"
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Constants.h"
#include "llvm/Function.h"
#include "llvm/DerivedTypes.h"
@ -470,7 +470,7 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
vector<MachineInstr*> loadConstVec;
MachineOpCode opCode = minstr->getOpCode();
const MachineInstrInfo& instrInfo = target.getInstrInfo();
const TargetInstrInfo& instrInfo = target.getInstrInfo();
int resultPos = instrInfo.getResultPos(opCode);
int immedPos = instrInfo.getImmedConstantPos(opCode);

2
lib/CodeGen/LiveVariables.cpp
View File

@ -6,7 +6,7 @@
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/CFG.h"
#include "Support/DepthFirstIterator.h"

6
lib/CodeGen/MachineInstr.cpp
View File

@ -6,19 +6,19 @@
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/Value.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/MRegisterInfo.h"
using std::cerr;
// Global variable holding an array of descriptors for machine instructions.
// The actual object needs to be created separately for each target machine.
// This variable is initialized and reset by class MachineInstrInfo.
// This variable is initialized and reset by class TargetInstrInfo.
//
// FIXME: This should be a property of the target so that more than one target
// at a time can be active...
//
extern const MachineInstrDescriptor *TargetInstrDescriptors;
extern const TargetInstrDescriptor *TargetInstrDescriptors;
// Constructor for instructions with fixed #operands (nearly all)
MachineInstr::MachineInstr(MachineOpCode _opCode)

2
lib/CodeGen/PHIElimination.cpp
View File

@ -10,7 +10,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
namespace {

10
lib/CodeGen/PrologEpilogInserter.cpp
View File

@ -16,7 +16,7 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
namespace {
struct PEI : public MachineFunctionPass {
@ -157,10 +157,10 @@ void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
}
// Add code to restore the callee-save registers in each exiting block.
const MachineInstrInfo &MII = Fn.getTarget().getInstrInfo();
const TargetInstrInfo &TII = Fn.getTarget().getInstrInfo();
for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI) {
// If last instruction is a return instruction, add an epilogue
if (MII.isReturn(FI->back()->getOpcode())) {
if (TII.isReturn(FI->back()->getOpcode())) {
MBB = FI; I = MBB->end()-1;
for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) {
@ -237,10 +237,10 @@ void PEI::insertPrologEpilogCode(MachineFunction &Fn) {
Fn.getTarget().getRegisterInfo()->emitPrologue(Fn);
// Add epilogue to restore the callee-save registers in each exiting block
const MachineInstrInfo &MII = Fn.getTarget().getInstrInfo();
const TargetInstrInfo &TII = Fn.getTarget().getInstrInfo();
for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
// If last instruction is a return instruction, add an epilogue
if (MII.isReturn(I->back()->getOpcode()))
if (TII.isReturn(I->back()->getOpcode()))
Fn.getTarget().getRegisterInfo()->emitEpilogue(Fn, *I);
}
}

2
lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
View File

@ -11,7 +11,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Function.h"
#include "Support/SetOperations.h"
using std::cerr;

2
lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
View File

@ -16,7 +16,7 @@
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Function.h"
#include "llvm/Type.h"
#include "llvm/iOther.h"

12
lib/CodeGen/RegAllocLocal.cpp
View File

@ -11,7 +11,7 @@
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "Support/Statistic.h"
#include "Support/CommandLine.h"
@ -442,11 +442,11 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
MachineBasicBlock::iterator I = MBB.begin();
for (; I != MBB.end(); ++I) {
MachineInstr *MI = *I;
const MachineInstrDescriptor &MID = TM->getInstrInfo().get(MI->getOpcode());
const TargetInstrDescriptor &TID = TM->getInstrInfo().get(MI->getOpcode());
// Loop over the implicit uses, making sure that they are at the head of the
// use order list, so they don't get reallocated.
if (const unsigned *ImplicitUses = MID.ImplicitUses)
if (const unsigned *ImplicitUses = TID.ImplicitUses)
for (unsigned i = 0; ImplicitUses[i]; ++i)
MarkPhysRegRecentlyUsed(ImplicitUses[i]);
@ -498,7 +498,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
}
// Loop over the implicit defs, spilling them as well.
if (const unsigned *ImplicitDefs = MID.ImplicitDefs)
if (const unsigned *ImplicitDefs = TID.ImplicitDefs)
for (unsigned i = 0; ImplicitDefs[i]; ++i) {
unsigned Reg = ImplicitDefs[i];
spillPhysReg(MBB, I, Reg);
@ -571,9 +571,9 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
}
// Rewind the iterator to point to the first flow control instruction...
const MachineInstrInfo &MII = TM->getInstrInfo();
const TargetInstrInfo &TII = TM->getInstrInfo();
I = MBB.end()-1;
while (I != MBB.begin() && MII.isTerminatorInstr((*(I-1))->getOpcode()))
while (I != MBB.begin() && TII.isTerminatorInstr((*(I-1))->getOpcode()))
--I;
// Spill all physical registers holding virtual registers now.

4
lib/CodeGen/RegAllocSimple.cpp
View File

@ -12,7 +12,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "Support/Statistic.h"
#include <iostream>
@ -150,7 +150,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
// a preliminary pass that will invalidate any registers that
// are used by the instruction (including implicit uses)
unsigned Opcode = MI->getOpcode();
const MachineInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode);
const TargetInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode);
if (const unsigned *Regs = Desc.ImplicitUses)
while (*Regs)
RegsUsed[*Regs++] = true;

12
lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
View File

@ -370,7 +370,7 @@ public:
// Simplify access to the machine instruction info
//----------------------------------------------------------------------
inline const MachineInstrInfo& getInstrInfo () const {
inline const TargetInstrInfo& getInstrInfo () const {
return schedInfo.getInstrInfo();
}
@ -630,7 +630,7 @@ AssignInstructionsToSlots(class SchedulingManager& S, unsigned maxIssue)
static void
RecordSchedule(MachineBasicBlock &MBB, const SchedulingManager& S)
{
const MachineInstrInfo& mii = S.schedInfo.getInstrInfo();
const TargetInstrInfo& mii = S.schedInfo.getInstrInfo();
#ifndef NDEBUG
// Lets make sure we didn't lose any instructions, except possibly
@ -1075,7 +1075,7 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
return false;
// don't put a load-use dependence in the delay slot of a branch
const MachineInstrInfo& mii = S.getInstrInfo();
const TargetInstrInfo& mii = S.getInstrInfo();
for (SchedGraphNode::const_iterator EI = node->beginInEdges();
EI != node->endInEdges(); ++EI)
@ -1143,7 +1143,7 @@ FindUsefulInstructionsForDelaySlots(SchedulingManager& S,
SchedGraphNode* brNode,
vector<SchedGraphNode*>& sdelayNodeVec)
{
const MachineInstrInfo& mii = S.getInstrInfo();
const TargetInstrInfo& mii = S.getInstrInfo();
unsigned ndelays =
mii.getNumDelaySlots(brNode->getOpCode());
@ -1207,7 +1207,7 @@ static void ReplaceNopsWithUsefulInstr(SchedulingManager& S,
SchedGraph* graph)
{
vector<SchedGraphNode*> nopNodeVec; // this will hold unused NOPs
const MachineInstrInfo& mii = S.getInstrInfo();
const TargetInstrInfo& mii = S.getInstrInfo();
const MachineInstr* brInstr = node->getMachineInstr();
unsigned ndelays= mii.getNumDelaySlots(brInstr->getOpCode());
assert(ndelays > 0 && "Unnecessary call to replace NOPs");
@ -1283,7 +1283,7 @@ static void
ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB,
SchedGraph *graph)
{
const MachineInstrInfo& mii = S.getInstrInfo();
const TargetInstrInfo& mii = S.getInstrInfo();
Instruction *termInstr = (Instruction*)MBB.getBasicBlock()->getTerminator();
MachineCodeForInstruction &termMvec=MachineCodeForInstruction::get(termInstr);

12
lib/Target/SparcV9/InstrSched/SchedGraph.cpp
View File

@ -12,7 +12,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetRegInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Function.h"
#include "llvm/iOther.h"
#include "Support/StringExtras.h"
@ -325,7 +325,7 @@ void
SchedGraph::addCDEdges(const TerminatorInst* term,
const TargetMachine& target)
{
const MachineInstrInfo& mii = target.getInstrInfo();
const TargetInstrInfo& mii = target.getInstrInfo();
MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
// Find the first branch instr in the sequence of machine instrs for term
@ -434,7 +434,7 @@ void
SchedGraph::addMemEdges(const vector<SchedGraphNode*>& memNodeVec,
const TargetMachine& target)
{
const MachineInstrInfo& mii = target.getInstrInfo();
const TargetInstrInfo& mii = target.getInstrInfo();
// Instructions in memNodeVec are in execution order within the basic block,
// so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
@ -471,7 +471,7 @@ SchedGraph::addCallCCEdges(const vector<SchedGraphNode*>& memNodeVec,
MachineBasicBlock& bbMvec,
const TargetMachine& target)
{
const MachineInstrInfo& mii = target.getInstrInfo();
const TargetInstrInfo& mii = target.getInstrInfo();
vector<SchedGraphNode*> callNodeVec;
// Find the call instruction nodes and put them in a vector.
@ -675,7 +675,7 @@ SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
RegToRefVecMap& regToRefVecMap,
ValueToDefVecMap& valueToDefVecMap)
{
const MachineInstrInfo& mii = target.getInstrInfo();
const TargetInstrInfo& mii = target.getInstrInfo();
MachineOpCode opCode = node->getOpCode();
@ -732,7 +732,7 @@ SchedGraph::buildNodesForBB(const TargetMachine& target,
RegToRefVecMap& regToRefVecMap,
ValueToDefVecMap& valueToDefVecMap)
{
const MachineInstrInfo& mii = target.getInstrInfo();
const TargetInstrInfo& mii = target.getInstrInfo();
// Build graph nodes for each VM instruction and gather def/use info.
// Do both those together in a single pass over all machine instructions.

4
lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
View File

@ -14,7 +14,7 @@
#include "llvm/CodeGen/InstrForest.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegInfo.h"
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Constants.h"
#include "llvm/Function.h"
#include "llvm/DerivedTypes.h"
@ -470,7 +470,7 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
vector<MachineInstr*> loadConstVec;
MachineOpCode opCode = minstr->getOpCode();
const MachineInstrInfo& instrInfo = target.getInstrInfo();
const TargetInstrInfo& instrInfo = target.getInstrInfo();
int resultPos = instrInfo.getResultPos(opCode);
int immedPos = instrInfo.getImmedConstantPos(opCode);

2
lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
View File

@ -11,7 +11,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Function.h"
#include "Support/SetOperations.h"
using std::cerr;

2
lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
View File

@ -16,7 +16,7 @@
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Function.h"
#include "llvm/Type.h"
#include "llvm/iOther.h"

2
lib/Target/SparcV9/SparcV9Instr.def
View File

@ -35,7 +35,7 @@
// numDelaySlots (in cycles)
// latency (in cycles)
// instr sched class (defined above)
// instr class flags (defined in MachineInstrInfo.h)
// instr class flags (defined in TargetInstrInfo.h)

8
lib/Target/SparcV9/SparcV9InstrInfo.cpp
View File

@ -321,14 +321,14 @@ InitializeMaxConstantsTable()
// Information about individual instructions.
// Most information is stored in the SparcMachineInstrDesc array above.
// Other information is computed on demand, and most such functions
// default to member functions in base class MachineInstrInfo.
// default to member functions in base class TargetInstrInfo.
//---------------------------------------------------------------------------
/*ctor*/
UltraSparcInstrInfo::UltraSparcInstrInfo()
: MachineInstrInfo(SparcMachineInstrDesc,
/*descSize = */ NUM_TOTAL_OPCODES,
/*numRealOpCodes = */ NUM_REAL_OPCODES)
: TargetInstrInfo(SparcMachineInstrDesc,
/*descSize = */ NUM_TOTAL_OPCODES,
/*numRealOpCodes = */ NUM_REAL_OPCODES)
{
InitializeMaxConstantsTable();
}

10
lib/Target/SparcV9/SparcV9Internals.h
View File

@ -41,7 +41,7 @@ enum SparcInstrSchedClass {
//---------------------------------------------------------------------------
// enum SparcMachineOpCode.
// const MachineInstrDescriptor SparcMachineInstrDesc[]
// const TargetInstrDescriptor SparcMachineInstrDesc[]
//
// Purpose:
// Description of UltraSparc machine instructions.
@ -62,7 +62,7 @@ enum SparcMachineOpCode {
// Array of machine instruction descriptions...
extern const MachineInstrDescriptor SparcMachineInstrDesc[];
extern const TargetInstrDescriptor SparcMachineInstrDesc[];
//---------------------------------------------------------------------------
@ -72,10 +72,10 @@ extern const MachineInstrDescriptor SparcMachineInstrDesc[];
// Information about individual instructions.
// Most information is stored in the SparcMachineInstrDesc array above.
// Other information is computed on demand, and most such functions
// default to member functions in base class MachineInstrInfo.
// default to member functions in base class TargetInstrInfo.
//---------------------------------------------------------------------------
struct UltraSparcInstrInfo : public MachineInstrInfo {
struct UltraSparcInstrInfo : public TargetInstrInfo {
UltraSparcInstrInfo();
//
@ -733,7 +733,7 @@ class UltraSparc : public TargetMachine {
public:
UltraSparc();
virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
virtual const TargetInstrInfo &getInstrInfo() const { return instrInfo; }
virtual const TargetSchedInfo &getSchedInfo() const { return schedInfo; }
virtual const TargetRegInfo &getRegInfo() const { return regInfo; }
virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; }

4
lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
View File

@ -9,7 +9,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOptInfo.h"
#include "llvm/BasicBlock.h"
#include "llvm/Pass.h"
@ -24,7 +24,7 @@ DeleteInstruction(MachineBasicBlock& mvec,
// Check if this instruction is in a delay slot of its predecessor.
if (BBI != mvec.begin())
{
const MachineInstrInfo& mii = target.getInstrInfo();
const TargetInstrInfo& mii = target.getInstrInfo();
MachineInstr* predMI = *(BBI-1);
if (unsigned ndelay = mii.getNumDelaySlots(predMI->getOpCode()))
{

2
lib/Target/SparcV9/SparcV9PreSelection.cpp
View File

@ -10,7 +10,7 @@
#include "llvm/CodeGen/PreSelection.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Support/InstVisitor.h"
#include "llvm/Module.h"

2
lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
View File

@ -96,7 +96,7 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF)
{
const TargetMachine &TM = MF.getTarget();
const MachineInstrInfo &MII = TM.getInstrInfo();
const TargetInstrInfo &MII = TM.getInstrInfo();
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
MachineBasicBlock &MBB = *I;

10
lib/Target/SparcV9/SparcV9StackSlots.cpp
View File

@ -8,16 +8,14 @@
#include "llvm/CodeGen/StackSlots.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Constant.h"
#include "llvm/Function.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Pass.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineFunctionInfo.h"
namespace {
class StackSlots : public FunctionPass {
class StackSlots : public MachineFunctionPass {
const TargetMachine &Target;
public:
StackSlots(const TargetMachine &T) : Target(T) {}
@ -30,12 +28,12 @@ namespace {
AU.setPreservesCFG();
}
bool runOnFunction(Function &F) {
bool runOnMachineFunction(MachineFunction &MF) {
const Type *PtrInt = PointerType::get(Type::IntTy);
unsigned Size = Target.getTargetData().getTypeSize(PtrInt);
Value *V = Constant::getNullValue(Type::IntTy);
MachineFunction::get(&F).getInfo()->allocateLocalVar(V, 2*Size);
MF.getInfo()->allocateLocalVar(V, 2*Size);
return true;
}
};

4
lib/Target/SparcV9/SparcV9TargetMachine.cpp
View File

@ -26,7 +26,7 @@ using std::cerr;
static const unsigned ImplicitRegUseList[] = { 0 }; /* not used yet */
// Build the MachineInstruction Description Array...
const MachineInstrDescriptor SparcMachineInstrDesc[] = {
const TargetInstrDescriptor SparcMachineInstrDesc[] = {
#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
{ OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
@ -124,7 +124,7 @@ UltraSparcFrameInfo::getDynamicAreaOffset(MachineFunction& mcInfo,
// Primary interface to machine description for the UltraSPARC.
// Primarily just initializes machine-dependent parameters in
// class TargetMachine, and creates machine-dependent subclasses
// for classes such as MachineInstrInfo.
// for classes such as TargetInstrInfo.
//
//---------------------------------------------------------------------------

2
lib/Target/TargetInstrInfo.cpp
View File

@ -3,7 +3,7 @@
//
//===----------------------------------------------------------------------===//
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Constant.h"
#include "llvm/DerivedTypes.h"

2
lib/Target/X86/FloatingPoint.cpp
View File

@ -10,7 +10,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "Support/Statistic.h"
#include <algorithm>

4
lib/Target/X86/InstSelectSimple.cpp
View File

@ -437,7 +437,7 @@ void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
/// the current one.
///
void ISel::SelectPHINodes() {
const MachineInstrInfo &MII = TM.getInstrInfo();
const TargetInstrInfo &TII = TM.getInstrInfo();
const Function &LF = *F->getFunction(); // The LLVM function...
for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
const BasicBlock *BB = I;
@ -468,7 +468,7 @@ void ISel::SelectPHINodes() {
//
MachineBasicBlock::iterator PI = PredMBB->end();
while (PI != PredMBB->begin() &&
MII.isTerminatorInstr((*(PI-1))->getOpcode()))
TII.isTerminatorInstr((*(PI-1))->getOpcode()))
--PI;
unsigned ValReg = getReg(PN->getIncomingValue(i), PredMBB, PI);
PhiMI->addRegOperand(ValReg);

4
lib/Target/X86/MachineCodeEmitter.cpp
View File

@ -220,7 +220,7 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI,
}
}
unsigned sizeOfPtr (const MachineInstrDescriptor &Desc) {
unsigned sizeOfPtr(const TargetInstrDescriptor &Desc) {
switch (Desc.TSFlags & X86II::ArgMask) {
case X86II::Arg8: return 1;
case X86II::Arg16: return 2;
@ -236,7 +236,7 @@ unsigned sizeOfPtr (const MachineInstrDescriptor &Desc) {
void Emitter::emitInstruction(MachineInstr &MI) {
unsigned Opcode = MI.getOpcode();
const MachineInstrDescriptor &Desc = II->get(Opcode);
const TargetInstrDescriptor &Desc = II->get(Opcode);
// Emit instruction prefixes if neccesary
if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...

8
lib/Target/X86/Printer.cpp
View File

@ -59,7 +59,7 @@ void Printer::printConstantPool(MachineConstantPool *MCP, const TargetData &TD){
bool Printer::runOnMachineFunction(MachineFunction &MF) {
static unsigned BBNumber = 0;
const TargetMachine &TM = MF.getTarget();
const MachineInstrInfo &MII = TM.getInstrInfo();
const TargetInstrInfo &TII = TM.getInstrInfo();
// Print out constants referenced by the function
printConstantPool(MF.getConstantPool(), TM.getTargetData());
@ -80,7 +80,7 @@ bool Printer::runOnMachineFunction(MachineFunction &MF) {
II != E; ++II) {
// Print the assembly for the instruction.
O << "\t";
MII.print(*II, O, TM);
TII.print(*II, O, TM);
}
}
@ -136,7 +136,7 @@ static void printOp(std::ostream &O, const MachineOperand &MO,
}
}
static const std::string sizePtr(const MachineInstrDescriptor &Desc) {
static const std::string sizePtr(const TargetInstrDescriptor &Desc) {
switch (Desc.TSFlags & X86II::ArgMask) {
default: assert(0 && "Unknown arg size!");
case X86II::Arg8: return "BYTE PTR";
@ -204,7 +204,7 @@ static void printMemReference(std::ostream &O, const MachineInstr *MI,
void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
const TargetMachine &TM) const {
unsigned Opcode = MI->getOpcode();
const MachineInstrDescriptor &Desc = get(Opcode);
const TargetInstrDescriptor &Desc = get(Opcode);
switch (Desc.TSFlags & X86II::FormMask) {
case X86II::Pseudo:

8
lib/Target/X86/X86AsmPrinter.cpp
View File

@ -59,7 +59,7 @@ void Printer::printConstantPool(MachineConstantPool *MCP, const TargetData &TD){
bool Printer::runOnMachineFunction(MachineFunction &MF) {
static unsigned BBNumber = 0;
const TargetMachine &TM = MF.getTarget();
const MachineInstrInfo &MII = TM.getInstrInfo();
const TargetInstrInfo &TII = TM.getInstrInfo();
// Print out constants referenced by the function
printConstantPool(MF.getConstantPool(), TM.getTargetData());
@ -80,7 +80,7 @@ bool Printer::runOnMachineFunction(MachineFunction &MF) {
II != E; ++II) {
// Print the assembly for the instruction.
O << "\t";
MII.print(*II, O, TM);
TII.print(*II, O, TM);
}
}
@ -136,7 +136,7 @@ static void printOp(std::ostream &O, const MachineOperand &MO,
}
}
static const std::string sizePtr(const MachineInstrDescriptor &Desc) {
static const std::string sizePtr(const TargetInstrDescriptor &Desc) {
switch (Desc.TSFlags & X86II::ArgMask) {
default: assert(0 && "Unknown arg size!");
case X86II::Arg8: return "BYTE PTR";
@ -204,7 +204,7 @@ static void printMemReference(std::ostream &O, const MachineInstr *MI,
void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
const TargetMachine &TM) const {
unsigned Opcode = MI->getOpcode();
const MachineInstrDescriptor &Desc = get(Opcode);
const TargetInstrDescriptor &Desc = get(Opcode);
switch (Desc.TSFlags & X86II::FormMask) {
case X86II::Pseudo:

4
lib/Target/X86/X86CodeEmitter.cpp
View File

@ -220,7 +220,7 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI,
}
}
unsigned sizeOfPtr (const MachineInstrDescriptor &Desc) {
unsigned sizeOfPtr(const TargetInstrDescriptor &Desc) {
switch (Desc.TSFlags & X86II::ArgMask) {
case X86II::Arg8: return 1;
case X86II::Arg16: return 2;
@ -236,7 +236,7 @@ unsigned sizeOfPtr (const MachineInstrDescriptor &Desc) {
void Emitter::emitInstruction(MachineInstr &MI) {
unsigned Opcode = MI.getOpcode();
const MachineInstrDescriptor &Desc = II->get(Opcode);
const TargetInstrDescriptor &Desc = II->get(Opcode);
// Emit instruction prefixes if neccesary
if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...

2
lib/Target/X86/X86FloatingPoint.cpp
View File

@ -10,7 +10,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "Support/Statistic.h"
#include <algorithm>

4
lib/Target/X86/X86ISelSimple.cpp
View File

@ -437,7 +437,7 @@ void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
/// the current one.
///
void ISel::SelectPHINodes() {
const MachineInstrInfo &MII = TM.getInstrInfo();
const TargetInstrInfo &TII = TM.getInstrInfo();
const Function &LF = *F->getFunction(); // The LLVM function...
for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
const BasicBlock *BB = I;
@ -468,7 +468,7 @@ void ISel::SelectPHINodes() {
//
MachineBasicBlock::iterator PI = PredMBB->end();
while (PI != PredMBB->begin() &&
MII.isTerminatorInstr((*(PI-1))->getOpcode()))
TII.isTerminatorInstr((*(PI-1))->getOpcode()))
--PI;
unsigned ValReg = getReg(PN->getIncomingValue(i), PredMBB, PI);
PhiMI->addRegOperand(ValReg);

6
lib/Target/X86/X86InstrInfo.cpp
View File

@ -1,6 +1,6 @@
//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
//
// This file contains the X86 implementation of the MachineInstrInfo class.
// This file contains the X86 implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
@ -17,7 +17,7 @@
// X86Insts - Turn the InstrInfo.def file into a bunch of instruction
// descriptors
//
static const MachineInstrDescriptor X86Insts[] = {
static const TargetInstrDescriptor X86Insts[] = {
#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPUSES, IMPDEFS) \
{ NAME, \
-1, /* Always vararg */ \
@ -35,7 +35,7 @@ static const MachineInstrDescriptor X86Insts[] = {
};
X86InstrInfo::X86InstrInfo()
: MachineInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) {
: TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) {
}

2
lib/Target/X86/X86InstrInfo.def
View File

@ -51,7 +51,7 @@ IMPREGSLIST(O_ST0, X86::ST0, 0)
// #2: Opcode name, as used by the gnu assembler
// #3: The base opcode for the instruction
// #4: Instruction Flags - This should be a field or'd together that contains
// constants from the MachineInstrInfo.h file.
// constants from the TargetInstrInfo.h file.
// #5: Target Specific Flags - Another bitfield containing X86 specific flags
// that we are interested in for each instruction. These should be flags
// defined in X86InstrInfo.h in the X86II namespace.

8
lib/Target/X86/X86InstrInfo.h
View File

@ -1,13 +1,13 @@
//===- X86InstructionInfo.h - X86 Instruction Information ---------*-C++-*-===//
//
// This file contains the X86 implementation of the MachineInstrInfo class.
// This file contains the X86 implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
#ifndef X86INSTRUCTIONINFO_H
#define X86INSTRUCTIONINFO_H
#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "X86RegisterInfo.h"
/// X86II - This namespace holds all of the target specific flags that
@ -137,12 +137,12 @@ namespace X86II {
};
}
class X86InstrInfo : public MachineInstrInfo {
class X86InstrInfo : public TargetInstrInfo {
const X86RegisterInfo RI;
public:
X86InstrInfo();
/// getRegisterInfo - MachineInstrInfo is a superset of MRegister info. As
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///