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https://github.com/c64scene-ar/llvm-6502.git
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Rename MachineInstrInfo -> TargetInstrInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5272 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -11,7 +11,7 @@
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/Target/MachineInstrInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "Support/Statistic.h"
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#include "Support/CommandLine.h"
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@ -442,11 +442,11 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
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MachineBasicBlock::iterator I = MBB.begin();
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for (; I != MBB.end(); ++I) {
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MachineInstr *MI = *I;
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const MachineInstrDescriptor &MID = TM->getInstrInfo().get(MI->getOpcode());
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const TargetInstrDescriptor &TID = TM->getInstrInfo().get(MI->getOpcode());
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// Loop over the implicit uses, making sure that they are at the head of the
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// use order list, so they don't get reallocated.
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if (const unsigned *ImplicitUses = MID.ImplicitUses)
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if (const unsigned *ImplicitUses = TID.ImplicitUses)
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for (unsigned i = 0; ImplicitUses[i]; ++i)
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MarkPhysRegRecentlyUsed(ImplicitUses[i]);
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@ -498,7 +498,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
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}
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// Loop over the implicit defs, spilling them as well.
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if (const unsigned *ImplicitDefs = MID.ImplicitDefs)
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if (const unsigned *ImplicitDefs = TID.ImplicitDefs)
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for (unsigned i = 0; ImplicitDefs[i]; ++i) {
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unsigned Reg = ImplicitDefs[i];
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spillPhysReg(MBB, I, Reg);
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@ -571,9 +571,9 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
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}
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// Rewind the iterator to point to the first flow control instruction...
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const MachineInstrInfo &MII = TM->getInstrInfo();
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const TargetInstrInfo &TII = TM->getInstrInfo();
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I = MBB.end()-1;
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while (I != MBB.begin() && MII.isTerminatorInstr((*(I-1))->getOpcode()))
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while (I != MBB.begin() && TII.isTerminatorInstr((*(I-1))->getOpcode()))
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--I;
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// Spill all physical registers holding virtual registers now.
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