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ARM: Implement CanLowerReturn so large vectors get expanded into sret.
Fixes 14337. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168809 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1882,6 +1882,17 @@ ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
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return true;
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return true;
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}
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}
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bool
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ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
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MachineFunction &MF, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const {
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
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return CCInfo.CheckReturn(Outs, CCAssignFnForNode(CallConv, /*Return=*/true,
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isVarArg));
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}
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SDValue
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SDValue
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ARMTargetLowering::LowerReturn(SDValue Chain,
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ARMTargetLowering::LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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CallingConv::ID CallConv, bool isVarArg,
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@ -495,6 +495,12 @@ namespace llvm {
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SelectionDAG& DAG) const;
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SelectionDAG& DAG) const;
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virtual bool CanLowerReturn(CallingConv::ID CallConv,
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MachineFunction &MF, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const;
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virtual SDValue
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virtual SDValue
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LowerReturn(SDValue Chain,
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LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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CallingConv::ID CallConv, bool isVarArg,
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12
test/CodeGen/ARM/ret_sret_vector.ll
Normal file
12
test/CodeGen/ARM/ret_sret_vector.ll
Normal file
@ -0,0 +1,12 @@
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; RUN: llc < %s | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
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target triple = "thumbv7-apple-ios3.0.0"
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define <4 x double> @PR14337(<4 x double> %a, <4 x double> %b) {
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%foo = fadd <4 x double> %a, %b
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ret <4 x double> %foo
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; CHECK: PR14337:
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; CHECK: vst1.64
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; CHECK: vst1.64
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}
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