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[mips] Refactor count leading zero or one instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170942 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-12-21 22:43:58 +00:00
parent 8aaed99a99
commit 35242e27c5
3 changed files with 29 additions and 20 deletions
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4
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -196,8 +196,8 @@ def SEB64 : SignExtInReg<"seb", i8, CPU64Regs>, SEB_FM<0x10>;
def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18>;
/// Count Leading
def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>;
def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>;
def DCLZ : CountLeading0<"dclz", CPU64Regs>, CLO_FM<0x24>;
def DCLO : CountLeading1<"dclo", CPU64Regs>, CLO_FM<0x25>;
/// Double Word Swap Bytes/HalfWords
def DSBH : SubwordSwap<0x24, 0x2, "dsbh", CPU64Regs>;

16
lib/Target/Mips/MipsInstrFormats.td
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@ -340,6 +340,22 @@ class SEB_FM<bits<5> funct> {
let Inst{5-0} = 0x20;
}
class CLO_FM<bits<6> funct> {
bits<5> rd;
bits<5> rs;
bits<5> rt;
bits<32> Inst;
let Inst{31-26} = 0x1c;
let Inst{25-21} = rs;
let Inst{20-16} = rt;
let Inst{15-11} = rd;
let Inst{10-6} = 0;
let Inst{5-0} = funct;
let rt = rd;
}
//===----------------------------------------------------------------------===//
//
// FLOATING POINT INSTRUCTION FORMATS

29
lib/Target/Mips/MipsInstrInfo.td
View File

@ -684,23 +684,16 @@ class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand
}
// Count Leading Ones/Zeros in Word
class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>:
FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
!strconcat(instr_asm, "\t$rd, $rs"),
[(set RC:$rd, (ctlz RC:$rs))], IIAlu>,
Requires<[HasBitCount, HasStdEnc]> {
let shamt = 0;
let rt = rd;
}
class CountLeading0<string opstr, RegisterClass RC>:
InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"),
[(set RC:$rd, (ctlz RC:$rs))], IIAlu, FrmR>,
Requires<[HasBitCount, HasStdEnc]>;
class CountLeading1<string opstr, RegisterClass RC>:
InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"),
[(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu, FrmR>,
Requires<[HasBitCount, HasStdEnc]>;
class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>:
FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
!strconcat(instr_asm, "\t$rd, $rs"),
[(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>,
Requires<[HasBitCount, HasStdEnc]> {
let shamt = 0;
let rt = rd;
}
// Sign Extend in Register.
class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> :
@ -966,8 +959,8 @@ def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10>;
def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18>;
/// Count Leading
def CLZ : CountLeading0<0x20, "clz", CPURegs>;
def CLO : CountLeading1<0x21, "clo", CPURegs>;
def CLZ : CountLeading0<"clz", CPURegs>, CLO_FM<0x20>;
def CLO : CountLeading1<"clo", CPURegs>, CLO_FM<0x21>;
/// Word Swap Bytes Within Halfwords
def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>;