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Simplify the tGPR register class now that the register allocators know not

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to try to allocate reserved registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112774 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-09-01 23:50:23 +00:00
parent d0b69cf119
commit 352f23529c
1 changed files with 1 additions and 26 deletions
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27
lib/Target/ARM/ARMRegisterInfo.td
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@ -425,32 +425,7 @@ def rGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
// Thumb registers are R0-R7 normally. Some instructions can still use
// the general GPR register class above (MOV, e.g.)
def tGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7]> {
let MethodProtos = [{
iterator allocation_order_begin(const MachineFunction &MF) const;
iterator allocation_order_end(const MachineFunction &MF) const;
}];
let MethodBodies = [{
static const unsigned THUMB_tGPR_AO[] = {
ARM::R0, ARM::R1, ARM::R2, ARM::R3,
ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
// FP is R7, only low registers available.
tGPRClass::iterator
tGPRClass::allocation_order_begin(const MachineFunction &MF) const {
return THUMB_tGPR_AO;
}
tGPRClass::iterator
tGPRClass::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
const TargetRegisterInfo *RI = TM.getRegisterInfo();
tGPRClass::iterator I =
THUMB_tGPR_AO + (sizeof(THUMB_tGPR_AO)/sizeof(unsigned));
return RI->hasFP(MF) ? I-1 : I;
}
}];
}
def tGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7]> {}
// For tail calls, we can't use callee-saved registers, as they are restored
// to the saved value before the tail call, which would clobber a call address.