From 355746359ebca83ccb5accab0f3ffd20f0374a35 Mon Sep 17 00:00:00 2001 From: Rafael Espindola Date: Tue, 18 Jul 2006 17:00:30 +0000 Subject: [PATCH] initial prologue and epilogue implementation. Need to define add and sub before finishing it :-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29175 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrInfo.td | 4 +++- lib/Target/ARM/ARMRegisterInfo.cpp | 20 ++++++++++++++++++++ 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 15a57c5a83d..4cf5acce849 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -53,7 +53,9 @@ def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt), "!ADJCALLSTACKDOWN $amt", [(callseq_start imm:$amt)]>; -def bxr: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>; +let isReturn = 1 in { + def bx: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>; +} def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>; diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index e7e1690596f..8daf0657948 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -116,10 +116,30 @@ void ARMRegisterInfo:: processFunctionBeforeFrameFinalized(MachineFunction &MF) const {} void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const { + MachineBasicBlock &MBB = MF.front(); + MachineFrameInfo *MFI = MF.getFrameInfo(); + int NumBytes = (int) MFI->getStackSize(); + + //hack + assert(NumBytes == 0); + + //add a sp = sp - 4 + BuildMI(MBB, MBB.begin(), ARM::str, 1, ARM::R14).addReg(ARM::R13); } void ARMRegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { + MachineBasicBlock::iterator MBBI = prior(MBB.end()); + assert(MBBI->getOpcode() == ARM::bx && + "Can only insert epilog into returning blocks"); + + MachineFrameInfo *MFI = MF.getFrameInfo(); + int NumBytes = (int) MFI->getStackSize(); + //hack + assert(NumBytes == 0); + + BuildMI(MBB, MBBI, ARM::ldr, 2, ARM::R14).addImm(0).addReg(ARM::R13); + //add a sp = sp + 4 } unsigned ARMRegisterInfo::getRARegister() const {