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R600/SI: Fix moveToVALU when the first operand is VSrc.

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Moving into a VSrc doesn't always work, since it could be
replaced with an SGPR later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195042 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2013-11-18 20:09:55 +00:00
parent 9bc4b2c0da
commit 3560dd2dcd
3 changed files with 14 additions and 13 deletions
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4
lib/Target/R600/SIInstrInfo.cpp
View File

@ -417,7 +417,6 @@ void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
MachineOperand &MO = MI->getOperand(OpIdx);
MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
// XXX - This shouldn't be VSrc
const TargetRegisterClass *RC = RI.getRegClass(RCID);
unsigned Opcode = AMDGPU::V_MOV_B32_e32;
if (MO.isReg()) {
@ -426,7 +425,8 @@ void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
Opcode = AMDGPU::S_MOV_B32;
}
unsigned Reg = MRI.createVirtualRegister(RI.getRegClass(RCID));
const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
unsigned Reg = MRI.createVirtualRegister(VRC);
BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
Reg).addOperand(MO);
MO.ChangeToRegister(Reg, false);

2
lib/Target/R600/SIRegisterInfo.cpp
View File

@ -100,6 +100,8 @@ const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
const TargetRegisterClass *SRC) const {
if (hasVGPRs(SRC)) {
return SRC;
} else if (SRC == &AMDGPU::SCCRegRegClass) {
return &AMDGPU::VCCRegRegClass;
} else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) {
return &AMDGPU::VReg_32RegClass;
} else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) {

21
test/CodeGen/R600/add_i64.ll
View File

@ -18,26 +18,25 @@ define void @test_i64_vreg(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noa
ret void
}
; SI-LABEL: @one_sgpr:
define void @one_sgpr(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 addrspace(1)* noalias %in_bar, i64 %a) {
; Check that the SGPR add operand is correctly moved to a VGPR.
; SI-LABEL: @sgpr_operand:
define void @sgpr_operand(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 addrspace(1)* noalias %in_bar, i64 %a) {
%foo = load i64 addrspace(1)* %in, align 8
%result = add i64 %foo, %a
store i64 %result, i64 addrspace(1)* %out
ret void
}
; FIXME: This case is broken
;
; Swap the arguments. Check that the SGPR -> VGPR copy works with the
; SGPR as other operand.
;
; XXXSI-LABEL: @one_sgpr_reversed:
; define void @one_sgpr_reversed(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %a) {
; %foo = load i64 addrspace(1)* %in, align 8
; %result = add i64 %a, %foo
; store i64 %result, i64 addrspace(1)* %out
; ret void
; }
; SI-LABEL: @sgpr_operand_reversed:
define void @sgpr_operand_reversed(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %a) {
%foo = load i64 addrspace(1)* %in, align 8
%result = add i64 %a, %foo
store i64 %result, i64 addrspace(1)* %out
ret void
}
; SI-LABEL: @test_v2i64_sreg: