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Part 1.

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- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2009-06-15 08:28:29 +00:00
parent d3b295c23f
commit 358dec5180
13 changed files with 613 additions and 141 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
lib/CodeGen/LiveInterval.cpp
View File

@@ -507,12 +507,11 @@ void LiveInterval::join(LiveInterval &Other, const int *LHSValNoAssignments,
// Update regalloc hint if currently there isn't one.
if (TargetRegisterInfo::isVirtualRegister(reg) &&
TargetRegisterInfo::isVirtualRegister(Other.reg)) {
std::pair<MachineRegisterInfo::RegAllocHintType, unsigned> Hint =
MRI->getRegAllocationHint(reg);
if (Hint.first == MachineRegisterInfo::RA_None) {
std::pair<MachineRegisterInfo::RegAllocHintType, unsigned> OtherHint =
std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(reg);
if (Hint.first == 0 && Hint.second == 0) {
std::pair<unsigned, unsigned> OtherHint =
MRI->getRegAllocationHint(Other.reg);
if (OtherHint.first != MachineRegisterInfo::RA_None)
if (OtherHint.first || OtherHint.second)
MRI->setRegAllocationHint(reg, OtherHint.first, OtherHint.second);
}
}
@@ -772,8 +771,7 @@ void LiveInterval::Copy(const LiveInterval &RHS,
BumpPtrAllocator &VNInfoAllocator) {
ranges.clear();
valnos.clear();
std::pair<MachineRegisterInfo::RegAllocHintType, unsigned> Hint =
MRI->getRegAllocationHint(RHS.reg);
std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(RHS.reg);
MRI->setRegAllocationHint(reg, Hint.first, Hint.second);
weight = RHS.weight;