mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-04 07:32:13 +00:00
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118199 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
d81f17acb4
commit
35b2de012d
@ -255,7 +255,7 @@ unsigned ARMMCCodeEmitter::getSORegOpValue(const MCInst &MI,
|
||||
// Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
|
||||
// shifted. The second is either Rs, the amount to shift by, or reg0 in which
|
||||
// case the imm contains the amount to shift by.
|
||||
//
|
||||
//
|
||||
// {3-0} = Rm.
|
||||
// {4} = 1 if reg shift, 0 if imm shift
|
||||
// {6-5} = type
|
||||
@ -349,7 +349,7 @@ unsigned ARMMCCodeEmitter::getAddrMode6AddressOpValue(const MCInst &MI,
|
||||
unsigned Op) const {
|
||||
const MCOperand &Reg = MI.getOperand(Op);
|
||||
const MCOperand &Imm = MI.getOperand(Op + 1);
|
||||
|
||||
|
||||
unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
|
||||
unsigned Align = 0;
|
||||
|
||||
|
Loading…
x
Reference in New Issue
Block a user