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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-02 07:11:49 +00:00
Added atomic 64 min/max/umin/umax instrinsics support in the ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168886 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Silviu Baranga
parent
5175fd990c
commit
35b3df6e31
@ -3327,6 +3327,15 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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return SelectAtomic64(N, ARM::ATOMSWAP6432);
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case ARMISD::ATOMCMPXCHG64_DAG:
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return SelectAtomic64(N, ARM::ATOMCMPXCHG6432);
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case ARMISD::ATOMMIN64_DAG:
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return SelectAtomic64(N, ARM::ATOMMIN6432);
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case ARMISD::ATOMUMIN64_DAG:
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return SelectAtomic64(N, ARM::ATOMUMIN6432);
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case ARMISD::ATOMMAX64_DAG:
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return SelectAtomic64(N, ARM::ATOMMAX6432);
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case ARMISD::ATOMUMAX64_DAG:
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return SelectAtomic64(N, ARM::ATOMUMAX6432);
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}
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return SelectCode(N);
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@ -695,7 +695,11 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
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// Automatically insert fences (dmb ist) around ATOMIC_SWAP etc.
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setInsertFencesForAtomic(true);
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@ -5406,6 +5410,18 @@ void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
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case ISD::ATOMIC_CMP_SWAP:
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ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMCMPXCHG64_DAG);
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return;
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case ISD::ATOMIC_LOAD_MIN:
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ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMMIN64_DAG);
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return;
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case ISD::ATOMIC_LOAD_UMIN:
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ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMUMIN64_DAG);
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return;
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case ISD::ATOMIC_LOAD_MAX:
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ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMMAX64_DAG);
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return;
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case ISD::ATOMIC_LOAD_UMAX:
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ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMUMAX64_DAG);
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return;
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}
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if (Res.getNode())
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Results.push_back(Res);
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@ -5745,7 +5761,8 @@ ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
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MachineBasicBlock *
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ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
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unsigned Op1, unsigned Op2,
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bool NeedsCarry, bool IsCmpxchg) const {
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bool NeedsCarry, bool IsCmpxchg,
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bool IsMinMax, ARMCC::CondCodes CC) const {
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// This also handles ATOMIC_SWAP, indicated by Op1==0.
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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@ -5774,16 +5791,15 @@ ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
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MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *contBB = 0, *cont2BB = 0;
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if (IsCmpxchg) {
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if (IsCmpxchg || IsMinMax)
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contBB = MF->CreateMachineBasicBlock(LLVM_BB);
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if (IsCmpxchg)
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cont2BB = MF->CreateMachineBasicBlock(LLVM_BB);
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}
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MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
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MF->insert(It, loopMBB);
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if (IsCmpxchg) {
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MF->insert(It, contBB);
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MF->insert(It, cont2BB);
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}
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if (IsCmpxchg || IsMinMax) MF->insert(It, contBB);
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if (IsCmpxchg) MF->insert(It, cont2BB);
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MF->insert(It, exitMBB);
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// Transfer the remainder of BB and its successor edges to exitMBB.
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@ -5821,6 +5837,22 @@ ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
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// Load
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unsigned GPRPair0 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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unsigned GPRPair1 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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unsigned GPRPair2;
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if (IsMinMax) {
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//We need an extra double register for doing min/max.
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unsigned undef = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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unsigned r1 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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GPRPair2 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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BuildMI(BB, dl, TII->get(TargetOpcode::IMPLICIT_DEF), undef);
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BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), r1)
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.addReg(undef)
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.addReg(vallo)
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.addImm(ARM::gsub_0);
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BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), GPRPair2)
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.addReg(r1)
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.addReg(valhi)
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.addImm(ARM::gsub_1);
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}
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AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc))
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.addReg(GPRPair0, RegState::Define).addReg(ptr));
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@ -5866,7 +5898,8 @@ ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
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.addReg(NeedsCarry ? ARM::CPSR : 0, getDefRegState(NeedsCarry));
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unsigned tmpRegHi = MRI.createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), tmpRegHi)
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.addReg(desthi).addReg(valhi)).addReg(0);
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.addReg(desthi).addReg(valhi))
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.addReg(IsMinMax ? ARM::CPSR : 0, getDefRegState(IsMinMax));
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unsigned UndefPair = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
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BuildMI(BB, dl, TII->get(TargetOpcode::IMPLICIT_DEF), UndefPair);
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@ -5893,10 +5926,20 @@ ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
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.addReg(valhi)
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.addImm(ARM::gsub_1);
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}
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unsigned GPRPairStore = GPRPair1;
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if (IsMinMax) {
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// Compare and branch to exit block.
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BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
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.addMBB(exitMBB).addImm(CC).addReg(ARM::CPSR);
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BB->addSuccessor(exitMBB);
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BB->addSuccessor(contBB);
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BB = contBB;
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GPRPairStore = GPRPair2;
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}
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// Store
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AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess)
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.addReg(GPRPair1).addReg(ptr));
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.addReg(GPRPairStore).addReg(ptr));
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// Cmp+jump
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AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
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.addReg(storesuccess).addImm(0));
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@ -6894,6 +6937,26 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
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isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
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/*NeedsCarry*/ false, /*IsCmpxchg*/true);
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case ARM::ATOMMIN6432:
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return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
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isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
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/*NeedsCarry*/ true, /*IsCmpxchg*/false,
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/*IsMinMax*/ true, ARMCC::LE);
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case ARM::ATOMMAX6432:
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return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
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isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
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/*NeedsCarry*/ true, /*IsCmpxchg*/false,
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/*IsMinMax*/ true, ARMCC::GE);
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case ARM::ATOMUMIN6432:
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return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
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isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
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/*NeedsCarry*/ true, /*IsCmpxchg*/false,
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/*IsMinMax*/ true, ARMCC::LS);
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case ARM::ATOMUMAX6432:
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return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
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isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
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/*NeedsCarry*/ true, /*IsCmpxchg*/false,
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/*IsMinMax*/ true, ARMCC::HS);
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case ARM::tMOVCCr_pseudo: {
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// To "insert" a SELECT_CC instruction, we actually have to insert the
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@ -232,7 +232,11 @@ namespace llvm {
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ATOMAND64_DAG,
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ATOMNAND64_DAG,
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ATOMSWAP64_DAG,
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ATOMCMPXCHG64_DAG
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ATOMCMPXCHG64_DAG,
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ATOMMIN64_DAG,
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ATOMUMIN64_DAG,
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ATOMMAX64_DAG,
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ATOMUMAX64_DAG
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};
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}
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@ -532,7 +536,9 @@ namespace llvm {
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unsigned Op1,
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unsigned Op2,
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bool NeedsCarry = false,
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bool IsCmpxchg = false) const;
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bool IsCmpxchg = false,
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bool IsMinMax = false,
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ARMCC::CondCodes CC = ARMCC::AL) const;
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MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
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MachineBasicBlock *BB,
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unsigned Size,
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@ -1624,6 +1624,18 @@ def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
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(ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
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GPR:$set1, GPR:$set2),
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NoItinerary, []>;
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def ATOMMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
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(ins GPR:$addr, GPR:$src1, GPR:$src2),
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NoItinerary, []>;
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def ATOMUMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
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(ins GPR:$addr, GPR:$src1, GPR:$src2),
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NoItinerary, []>;
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def ATOMMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
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(ins GPR:$addr, GPR:$src1, GPR:$src2),
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NoItinerary, []>;
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def ATOMUMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
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(ins GPR:$addr, GPR:$src1, GPR:$src2),
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NoItinerary, []>;
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}
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def HINT : AI<(outs), (ins imm0_255:$imm), MiscFrm, NoItinerary,
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@ -126,3 +126,64 @@ define void @test9(i64* %ptr, i64 %val) {
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store atomic i64 %val, i64* %ptr seq_cst, align 8
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ret void
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}
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define i64 @test10(i64* %ptr, i64 %val) {
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; CHECK: test10:
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; CHECK: dmb ish
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
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; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
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; CHECK: ble
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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%r = atomicrmw min i64* %ptr, i64 %val seq_cst
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ret i64 %r
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}
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define i64 @test11(i64* %ptr, i64 %val) {
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; CHECK: test11:
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; CHECK: dmb ish
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
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; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
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; CHECK: bls
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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%r = atomicrmw umin i64* %ptr, i64 %val seq_cst
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ret i64 %r
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}
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define i64 @test12(i64* %ptr, i64 %val) {
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; CHECK: test12:
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; CHECK: dmb ish
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
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; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
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; CHECK: bge
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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%r = atomicrmw max i64* %ptr, i64 %val seq_cst
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ret i64 %r
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}
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define i64 @test13(i64* %ptr, i64 %val) {
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; CHECK: test13:
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; CHECK: dmb ish
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
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; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
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; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
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; CHECK: bhs
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; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
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; CHECK: cmp
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; CHECK: bne
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; CHECK: dmb ish
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%r = atomicrmw umax i64* %ptr, i64 %val seq_cst
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ret i64 %r
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}
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