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[ARM64] Change SYS without a register to an alias to make disassembling more consistant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205898 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -774,22 +774,6 @@ def sys_cr_op : Operand<i32> {
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let ParserMatchClass = SysCRAsmOperand;
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}
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class SystemI<bit L, string asm>
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: SimpleSystemI<L,
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(ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2),
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asm, "\t$op1, $Cn, $Cm, $op2">,
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Sched<[WriteSys]> {
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bits<3> op1;
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bits<4> Cn;
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bits<4> Cm;
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bits<3> op2;
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let Inst{20-19} = 0b01;
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let Inst{18-16} = op1;
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let Inst{15-12} = Cn;
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let Inst{11-8} = Cm;
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let Inst{7-5} = op2;
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}
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class SystemXtI<bit L, string asm>
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: RtSystemI<L, (outs),
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(ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, GPR64:$Rt),
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@ -332,10 +332,13 @@ def MSRcpsr: MSRcpsrI;
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def : Pat<(ARM64threadpointer), (MRS 0xde82)>;
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// Generic system instructions
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def SYS : SystemI<0, "sys">;
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def SYSxt : SystemXtI<0, "sys">;
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def SYSLxt : SystemLXtI<1, "sysl">;
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def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
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(SYSxt imm0_7:$op1, sys_cr_op:$Cn,
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sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
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//===----------------------------------------------------------------------===//
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// Move immediate instructions.
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//===----------------------------------------------------------------------===//
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@ -56,7 +56,7 @@ void ARM64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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unsigned Opcode = MI->getOpcode();
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if (Opcode == ARM64::SYS || Opcode == ARM64::SYSxt)
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if (Opcode == ARM64::SYSxt)
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if (printSysAlias(MI, O)) {
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printAnnotation(O, Annot);
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return;
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@ -750,8 +750,7 @@ void ARM64AppleInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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bool ARM64InstPrinter::printSysAlias(const MCInst *MI, raw_ostream &O) {
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#ifndef NDEBUG
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unsigned Opcode = MI->getOpcode();
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assert((Opcode == ARM64::SYS || Opcode == ARM64::SYSxt) &&
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"Invalid opcode for SYS alias!");
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assert(Opcode == ARM64::SYSxt && "Invalid opcode for SYS alias!");
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#endif
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const char *Asm = 0;
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@ -961,9 +960,11 @@ bool ARM64InstPrinter::printSysAlias(const MCInst *MI, raw_ostream &O) {
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}
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if (Asm) {
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unsigned Reg = MI->getOperand(4).getReg();
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O << '\t' << Asm;
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if (MI->getNumOperands() == 5)
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O << ", " << getRegisterName(MI->getOperand(4).getReg());
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if (StringRef(Asm).lower().find("all") == StringRef::npos)
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O << ", " << getRegisterName(Reg);
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}
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return Asm != 0;
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@ -32,6 +32,8 @@
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# CHECK: dmb osh
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0x9f 0x37 0x03 0xd5
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# CHECK: dsb nsh
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0x3f 0x76 0x08 0xd5
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# CHECK: dc ivac
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#-----------------------------------------------------------------------------
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# Generic system instructions
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