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use proper (82-bit) spills/fills when spilling FP regs, so that

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divides don't get broken. this fixes obsequi, smg2000, and probably
a bunch of other stuff (tm)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25385 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duraid Madina 2006-01-17 02:04:52 +00:00
parent ae6dcddcfe
commit 362071d7d4
3 changed files with 11 additions and 3 deletions
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4
lib/Target/IA64/IA64InstrInfo.td
View File

@ -537,6 +537,8 @@ let isStore = 1, noResults = 1 in {
"stfs [$dstPtr] = $value;;">;
def STF8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
"stfd [$dstPtr] = $value;;">;
def STF_SPILL : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
"stf.spill [$dstPtr] = $value;;">;
}
let isLoad = 1 in {
@ -552,6 +554,8 @@ let isLoad = 1 in {
"ldfs $dst = [$srcPtr];;">;
def LDF8 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
"ldfd $dst = [$srcPtr];;">;
def LDF_FILL : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
"ldf.fill $dst = [$srcPtr];;">;
}
def POPCNT : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src),

4
lib/Target/IA64/IA64RegisterInfo.cpp
View File

@ -40,7 +40,7 @@ void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
const TargetRegisterClass *RC) const{
if (RC == IA64::FPRegisterClass) {
BuildMI(MBB, MI, IA64::STF8, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
BuildMI(MBB, MI, IA64::STF_SPILL, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
} else if (RC == IA64::GRRegisterClass) {
BuildMI(MBB, MI, IA64::ST8, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
}
@ -63,7 +63,7 @@ void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
const TargetRegisterClass *RC)const{
if (RC == IA64::FPRegisterClass) {
BuildMI(MBB, MI, IA64::LDF8, 1, DestReg).addFrameIndex(FrameIdx);
BuildMI(MBB, MI, IA64::LDF_FILL, 1, DestReg).addFrameIndex(FrameIdx);
} else if (RC == IA64::GRRegisterClass) {
BuildMI(MBB, MI, IA64::LD8, 1, DestReg).addFrameIndex(FrameIdx);
} else if (RC == IA64::PRRegisterClass) {

6
lib/Target/IA64/IA64RegisterInfo.td
View File

@ -282,7 +282,11 @@ def GR : RegisterClass<"IA64", [i64], 64,
// these are the scratch (+stacked) FP registers
def FP : RegisterClass<"IA64", [f64], 64,
// the 128 here is to make stf.spill/ldf.fill happy,
// when storing full (82-bit) FP regs to stack slots
// we need to 16-byte align
def FP : RegisterClass<"IA64", [f64], 128,
[F6, F7,
F8, F9, F10, F11, F12, F13, F14, F15,
F32, F33, F34, F35, F36, F37, F38, F39,