6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-11-01 15:17:25 +00:00
Code Issues Projects Releases Wiki Activity

Rework the SelectionDAG-based implementations of SimplifyDemandedBits

Browse Source 
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26238 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
2006-02-16 21:11:51 +00:00
parent a6bbfe8448
commit 368e18d56a
7 changed files with 639 additions and 215 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
lib/Target/X86/X86ISelLowering.cpp
View File

@@ -2035,19 +2035,23 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
}
}
bool X86TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op,
uint64_t Mask) const {
void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
uint64_t Mask,
uint64_t &KnownZero,
uint64_t &KnownOne,
unsigned Depth) const {
unsigned Opc = Op.getOpcode();
KnownZero = KnownOne = 0; // Don't know anything.
switch (Opc) {
default:
assert(Opc >= ISD::BUILTIN_OP_END && "Expected a target specific node");
break;
case X86ISD::SETCC: return (Mask & 1) == 0;
case X86ISD::SETCC:
KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
break;
}
return false;
}
std::vector<unsigned> X86TargetLowering::