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[FastISel][AArch64] Teach the address computation to also fold sub instructions.

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Tiny enhancement to the address computation code to also fold sub instructions
if the rhs is constant and can be folded into the offset.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219186 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka 2014-10-07 03:40:03 +00:00
parent ca07e256f6
commit 3692081566
2 changed files with 22 additions and 11 deletions
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13
lib/Target/AArch64/AArch64FastISel.cpp
View File

@ -590,7 +590,7 @@ bool AArch64FastISel::computeAddress(const Value *Obj, Address &Addr, Type *Ty)
std::swap(LHS, RHS);
if (const ConstantInt *CI = dyn_cast<ConstantInt>(RHS)) {
Addr.setOffset(Addr.getOffset() + (uint64_t)CI->getSExtValue());
Addr.setOffset(Addr.getOffset() + CI->getSExtValue());
return computeAddress(LHS, Addr, Ty);
}
@ -601,6 +601,17 @@ bool AArch64FastISel::computeAddress(const Value *Obj, Address &Addr, Type *Ty)
break;
}
case Instruction::Sub: {
// Subs of constants are common and easy enough.
const Value *LHS = U->getOperand(0);
const Value *RHS = U->getOperand(1);
if (const ConstantInt *CI = dyn_cast<ConstantInt>(RHS)) {
Addr.setOffset(Addr.getOffset() - CI->getSExtValue());
return computeAddress(LHS, Addr, Ty);
}
break;
}
case Instruction::Shl: {
if (Addr.getOffsetReg())
break;

20
test/CodeGen/AArch64/fast-isel-int-ext.ll
View File

@ -151,7 +151,7 @@ define i32 @load_unscaled_zext_i8_to_i32(i64 %a) {
; CHECK-LABEL: load_unscaled_zext_i8_to_i32
; CHECK: ldurb w0, [x0, #-8]
; CHECK-NOT: uxtb
%1 = add i64 %a, -8
%1 = sub i64 %a, 8
%2 = inttoptr i64 %1 to i8*
%3 = load i8* %2
%4 = zext i8 %3 to i32
@ -162,7 +162,7 @@ define i32 @load_unscaled_zext_i16_to_i32(i64 %a) {
; CHECK-LABEL: load_unscaled_zext_i16_to_i32
; CHECK: ldurh w0, [x0, #-8]
; CHECK-NOT: uxth
%1 = add i64 %a, -8
%1 = sub i64 %a, 8
%2 = inttoptr i64 %1 to i16*
%3 = load i16* %2
%4 = zext i16 %3 to i32
@ -173,7 +173,7 @@ define i64 @load_unscaled_zext_i8_to_i64(i64 %a) {
; CHECK-LABEL: load_unscaled_zext_i8_to_i64
; CHECK: ldurb w0, [x0, #-8]
; CHECK-NOT: uxtb
%1 = add i64 %a, -8
%1 = sub i64 %a, 8
%2 = inttoptr i64 %1 to i8*
%3 = load i8* %2
%4 = zext i8 %3 to i64
@ -184,7 +184,7 @@ define i64 @load_unscaled_zext_i16_to_i64(i64 %a) {
; CHECK-LABEL: load_unscaled_zext_i16_to_i64
; CHECK: ldurh w0, [x0, #-8]
; CHECK-NOT: uxth
%1 = add i64 %a, -8
%1 = sub i64 %a, 8
%2 = inttoptr i64 %1 to i16*
%3 = load i16* %2
%4 = zext i16 %3 to i64
@ -195,7 +195,7 @@ define i64 @load_unscaled_zext_i32_to_i64(i64 %a) {
; CHECK-LABEL: load_unscaled_zext_i32_to_i64
; CHECK: ldur w0, [x0, #-8]
; CHECK-NOT: uxtw
%1 = add i64 %a, -8
%1 = sub i64 %a, 8
%2 = inttoptr i64 %1 to i32*
%3 = load i32* %2
%4 = zext i32 %3 to i64
@ -206,7 +206,7 @@ define i32 @load_unscaled_sext_i8_to_i32(i64 %a) {
; CHECK-LABEL: load_unscaled_sext_i8_to_i32
; CHECK: ldursb w0, [x0, #-8]
; CHECK-NOT: sxtb
%1 = add i64 %a, -8
%1 = sub i64 %a, 8
%2 = inttoptr i64 %1 to i8*
%3 = load i8* %2
%4 = sext i8 %3 to i32
@ -217,7 +217,7 @@ define i32 @load_unscaled_sext_i16_to_i32(i64 %a) {
; CHECK-LABEL: load_unscaled_sext_i16_to_i32
; CHECK: ldursh w0, [x0, #-8]
; CHECK-NOT: sxth
%1 = add i64 %a, -8
%1 = sub i64 %a, 8
%2 = inttoptr i64 %1 to i16*
%3 = load i16* %2
%4 = sext i16 %3 to i32
@ -228,7 +228,7 @@ define i64 @load_unscaled_sext_i8_to_i64(i64 %a) {
; CHECK-LABEL: load_unscaled_sext_i8_to_i64
; CHECK: ldursb x0, [x0, #-8]
; CHECK-NOT: sxtb
%1 = add i64 %a, -8
%1 = sub i64 %a, 8
%2 = inttoptr i64 %1 to i8*
%3 = load i8* %2
%4 = sext i8 %3 to i64
@ -239,7 +239,7 @@ define i64 @load_unscaled_sext_i16_to_i64(i64 %a) {
; CHECK-LABEL: load_unscaled_sext_i16_to_i64
; CHECK: ldursh x0, [x0, #-8]
; CHECK-NOT: sxth
%1 = add i64 %a, -8
%1 = sub i64 %a, 8
%2 = inttoptr i64 %1 to i16*
%3 = load i16* %2
%4 = sext i16 %3 to i64
@ -250,7 +250,7 @@ define i64 @load_unscaled_sext_i32_to_i64(i64 %a) {
; CHECK-LABEL: load_unscaled_sext_i32_to_i64
; CHECK: ldursw x0, [x0, #-8]
; CHECK-NOT: sxtw
%1 = add i64 %a, -8
%1 = sub i64 %a, 8
%2 = inttoptr i64 %1 to i32*
%3 = load i32* %2
%4 = sext i32 %3 to i64