From 3717ca965bcfb6c66d7e9016566be842a9cc5629 Mon Sep 17 00:00:00 2001
From: Rafael Espindola <rafael.espindola@gmail.com>
Date: Sun, 20 Aug 2006 01:49:49 +0000
Subject: [PATCH] call computeRegisterProperties

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29780 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMISelDAGToDAG.cpp | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 56d61165c3c..cf23f2a4409 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -42,11 +42,17 @@ namespace {
 
 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
   : TargetLowering(TM) {
+  addRegisterClass(MVT::i32, ARM::IntRegsRegisterClass);
+
+  //LLVM requires that a register class supports MVT::f64!
+  addRegisterClass(MVT::f64, ARM::IntRegsRegisterClass);
+
   setOperationAction(ISD::RET,           MVT::Other, Custom);
   setOperationAction(ISD::GlobalAddress, MVT::i32,   Custom);
   setOperationAction(ISD::ConstantPool,  MVT::i32,   Custom);
 
   setSchedulingPreference(SchedulingForRegPressure);
+  computeRegisterProperties();
 }
 
 namespace llvm {