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Move all of the ARM subtarget features down onto the subtarget

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rather than the target machine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211799 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2014-06-26 19:30:02 +00:00
parent 1bb7dd619d
commit 373c16a702
4 changed files with 102 additions and 121 deletions
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26
lib/Target/ARM/ARMSubtarget.cpp
View File

@ -12,8 +12,15 @@
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "ARMSubtarget.h" #include "ARMSubtarget.h"
#include "ARMBaseInstrInfo.h" #include "ARMFrameLowering.h"
#include "ARMBaseRegisterInfo.h" #include "ARMISelLowering.h"
#include "ARMInstrInfo.h"
#include "ARMJITInfo.h"
#include "ARMSelectionDAGInfo.h"
#include "ARMSubtarget.h"
#include "Thumb1FrameLowering.h"
#include "Thumb1InstrInfo.h"
#include "Thumb2InstrInfo.h"
#include "llvm/IR/Attributes.h" #include "llvm/IR/Attributes.h"
#include "llvm/IR/Function.h" #include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h" #include "llvm/IR/GlobalValue.h"
@ -142,13 +149,22 @@ ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
} }
ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool IsLittle, const std::string &FS, TargetMachine &TM,
const TargetOptions &Options) bool IsLittle, const TargetOptions &Options)
: ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others), : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle), ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle),
TargetTriple(TT), Options(Options), TargetABI(ARM_ABI_UNKNOWN), TargetTriple(TT), Options(Options), TargetABI(ARM_ABI_UNKNOWN),
DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS))), DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS))),
TSInfo(DL), JITInfo() {} TSInfo(DL), JITInfo(),
InstrInfo(isThumb1Only()
? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
: !isThumb()
? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
: (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
TLInfo(TM),
FrameLowering(!isThumb1Only()
? new ARMFrameLowering(*this)
: (ARMFrameLowering *)new Thumb1FrameLowering(*this)) {}
void ARMSubtarget::initializeEnvironment() { void ARMSubtarget::initializeEnvironment() {
HasV4TOps = false; HasV4TOps = false;

22
lib/Target/ARM/ARMSubtarget.h
View File

@ -14,8 +14,17 @@
#ifndef ARMSUBTARGET_H #ifndef ARMSUBTARGET_H
#define ARMSUBTARGET_H #define ARMSUBTARGET_H
#include "ARMFrameLowering.h"
#include "ARMISelLowering.h"
#include "ARMInstrInfo.h"
#include "ARMJITInfo.h" #include "ARMJITInfo.h"
#include "ARMSelectionDAGInfo.h" #include "ARMSelectionDAGInfo.h"
#include "ARMSubtarget.h"
#include "Thumb1FrameLowering.h"
#include "Thumb1InstrInfo.h"
#include "Thumb2InstrInfo.h"
#include "ARMJITInfo.h"
#include "MCTargetDesc/ARMMCTargetDesc.h" #include "MCTargetDesc/ARMMCTargetDesc.h"
#include "llvm/ADT/Triple.h" #include "llvm/ADT/Triple.h"
#include "llvm/IR/DataLayout.h" #include "llvm/IR/DataLayout.h"
@ -236,7 +245,7 @@ protected:
/// of the specified triple. /// of the specified triple.
/// ///
ARMSubtarget(const std::string &TT, const std::string &CPU, ARMSubtarget(const std::string &TT, const std::string &CPU,
const std::string &FS, bool IsLittle, const std::string &FS, TargetMachine &TM, bool IsLittle,
const TargetOptions &Options); const TargetOptions &Options);
/// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
@ -258,11 +267,22 @@ protected:
const DataLayout *getDataLayout() const { return &DL; } const DataLayout *getDataLayout() const { return &DL; }
const ARMSelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; } const ARMSelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; }
ARMJITInfo *getJITInfo() { return &JITInfo; } ARMJITInfo *getJITInfo() { return &JITInfo; }
const ARMBaseInstrInfo *getInstrInfo() const { return InstrInfo.get(); }
const ARMTargetLowering *getTargetLowering() const { return &TLInfo; }
const ARMFrameLowering *getFrameLowering() const { return FrameLowering.get(); }
const ARMBaseRegisterInfo *getRegisterInfo() const {
return &InstrInfo->getRegisterInfo();
}
private: private:
const DataLayout DL; const DataLayout DL;
ARMSelectionDAGInfo TSInfo; ARMSelectionDAGInfo TSInfo;
ARMJITInfo JITInfo; ARMJITInfo JITInfo;
// Either Thumb1InstrInfo or Thumb2InstrInfo.
std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
ARMTargetLowering TLInfo;
// Either Thumb1FrameLowering or ARMFrameLowering.
std::unique_ptr<ARMFrameLowering> FrameLowering;
void initializeEnvironment(); void initializeEnvironment();
void resetSubtargetFeatures(StringRef CPU, StringRef FS); void resetSubtargetFeatures(StringRef CPU, StringRef FS);

55
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -49,10 +49,9 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, CodeGenOpt::Level OL, bool isLittle)
bool isLittle)
: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
Subtarget(TT, CPU, FS, isLittle, Options) { Subtarget(TT, CPU, FS, *this, isLittle, Options) {
// Default to triple-appropriate float ABI // Default to triple-appropriate float ABI
if (Options.FloatABIType == FloatABI::Default) if (Options.FloatABIType == FloatABI::Default)
@ -71,16 +70,11 @@ void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
void ARMTargetMachine::anchor() { } void ARMTargetMachine::anchor() { }
ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU,
StringRef CPU, StringRef FS, StringRef FS, const TargetOptions &Options,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, CodeGenOpt::Level OL, bool isLittle)
bool isLittle) : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle),
InstrInfo(Subtarget),
TLInfo(*this),
FrameLowering(Subtarget) {
initAsmInfo(); initAsmInfo();
if (!Subtarget.hasARMOps()) if (!Subtarget.hasARMOps())
report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not " report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
@ -89,18 +83,18 @@ ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
void ARMLETargetMachine::anchor() { } void ARMLETargetMachine::anchor() { }
ARMLETargetMachine:: ARMLETargetMachine::ARMLETargetMachine(const Target &T, StringRef TT,
ARMLETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
StringRef CPU, StringRef FS, const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
void ARMBETargetMachine::anchor() { } void ARMBETargetMachine::anchor() { }
ARMBETargetMachine:: ARMBETargetMachine::ARMBETargetMachine(const Target &T, StringRef TT,
ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
StringRef CPU, StringRef FS, const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
@ -111,33 +105,26 @@ ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
StringRef CPU, StringRef FS, StringRef CPU, StringRef FS,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, CodeGenOpt::Level OL, bool isLittle)
bool isLittle) : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL,
: ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle), isLittle) {
InstrInfo(Subtarget.hasThumb2()
? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
: ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
TLInfo(*this),
FrameLowering(Subtarget.hasThumb2()
? new ARMFrameLowering(Subtarget)
: (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
initAsmInfo(); initAsmInfo();
} }
void ThumbLETargetMachine::anchor() { } void ThumbLETargetMachine::anchor() { }
ThumbLETargetMachine:: ThumbLETargetMachine::ThumbLETargetMachine(const Target &T, StringRef TT,
ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
StringRef CPU, StringRef FS, const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
void ThumbBETargetMachine::anchor() { } void ThumbBETargetMachine::anchor() { }
ThumbBETargetMachine:: ThumbBETargetMachine::ThumbBETargetMachine(const Target &T, StringRef TT,
ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
StringRef CPU, StringRef FS, const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}

90
lib/Target/ARM/ARMTargetMachine.h
View File

@ -41,9 +41,20 @@ public:
bool isLittle); bool isLittle);
const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; } const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
const ARMBaseRegisterInfo *getRegisterInfo() const override {
return getSubtargetImpl()->getRegisterInfo();
}
const ARMTargetLowering *getTargetLowering() const override { const ARMTargetLowering *getTargetLowering() const override {
// Implemented by derived classes return getSubtargetImpl()->getTargetLowering();
llvm_unreachable("getTargetLowering not implemented"); }
const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
return getSubtargetImpl()->getSelectionDAGInfo();
}
const ARMBaseInstrInfo *getInstrInfo() const override {
return getSubtargetImpl()->getInstrInfo();
}
const ARMFrameLowering *getFrameLowering() const override {
return getSubtargetImpl()->getFrameLowering();
} }
const InstrItineraryData *getInstrItineraryData() const override { const InstrItineraryData *getInstrItineraryData() const override {
return &getSubtargetImpl()->getInstrItineraryData(); return &getSubtargetImpl()->getInstrItineraryData();
@ -66,32 +77,10 @@ public:
/// ///
class ARMTargetMachine : public ARMBaseTargetMachine { class ARMTargetMachine : public ARMBaseTargetMachine {
virtual void anchor(); virtual void anchor();
ARMInstrInfo InstrInfo;
ARMTargetLowering TLInfo;
ARMFrameLowering FrameLowering;
public: public:
ARMTargetMachine(const Target &T, StringRef TT, ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM,
const TargetOptions &Options, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL,
bool isLittle);
const ARMRegisterInfo *getRegisterInfo() const override {
return &InstrInfo.getRegisterInfo();
}
const ARMTargetLowering *getTargetLowering() const override {
return &TLInfo;
}
const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
return getSubtargetImpl()->getSelectionDAGInfo();
}
const ARMFrameLowering *getFrameLowering() const override {
return &FrameLowering;
}
const ARMInstrInfo *getInstrInfo() const override { return &InstrInfo; }
}; };
/// ARMLETargetMachine - ARM little endian target machine. /// ARMLETargetMachine - ARM little endian target machine.
@ -110,10 +99,9 @@ public:
class ARMBETargetMachine : public ARMTargetMachine { class ARMBETargetMachine : public ARMTargetMachine {
void anchor() override; void anchor() override;
public: public:
ARMBETargetMachine(const Target &T, StringRef TT, ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
StringRef CPU, StringRef FS, const TargetOptions &Options, const TargetOptions &Options, Reloc::Model RM,
Reloc::Model RM, CodeModel::Model CM, CodeModel::Model CM, CodeGenOpt::Level OL);
CodeGenOpt::Level OL);
}; };
/// ThumbTargetMachine - Thumb target machine. /// ThumbTargetMachine - Thumb target machine.
@ -122,40 +110,10 @@ public:
/// ///
class ThumbTargetMachine : public ARMBaseTargetMachine { class ThumbTargetMachine : public ARMBaseTargetMachine {
virtual void anchor(); virtual void anchor();
// Either Thumb1InstrInfo or Thumb2InstrInfo.
std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
ARMTargetLowering TLInfo;
// Either Thumb1FrameLowering or ARMFrameLowering.
std::unique_ptr<ARMFrameLowering> FrameLowering;
public: public:
ThumbTargetMachine(const Target &T, StringRef TT, ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM,
const TargetOptions &Options, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL,
bool isLittle);
/// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
const ARMBaseRegisterInfo *getRegisterInfo() const override {
return &InstrInfo->getRegisterInfo();
}
const ARMTargetLowering *getTargetLowering() const override {
return &TLInfo;
}
const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
return getSubtargetImpl()->getSelectionDAGInfo();
}
/// returns either Thumb1InstrInfo or Thumb2InstrInfo
const ARMBaseInstrInfo *getInstrInfo() const override {
return InstrInfo.get();
}
/// returns either Thumb1FrameLowering or ARMFrameLowering
const ARMFrameLowering *getFrameLowering() const override {
return FrameLowering.get();
}
}; };
/// ThumbLETargetMachine - Thumb little endian target machine. /// ThumbLETargetMachine - Thumb little endian target machine.
@ -163,8 +121,8 @@ public:
class ThumbLETargetMachine : public ThumbTargetMachine { class ThumbLETargetMachine : public ThumbTargetMachine {
void anchor() override; void anchor() override;
public: public:
ThumbLETargetMachine(const Target &T, StringRef TT, ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU,
StringRef CPU, StringRef FS, const TargetOptions &Options, StringRef FS, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
}; };