From 374b36d5cf56e070ed7a557314616fc48711d8ea Mon Sep 17 00:00:00 2001 From: Brian Gaeke Date: Wed, 29 Sep 2004 20:45:05 +0000 Subject: [PATCH] Tell the target description that calls clobber registers O0...O5. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16594 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Sparc/SparcInstrInfo.td | 19 +++++++++---------- lib/Target/SparcV8/SparcV8InstrInfo.td | 19 +++++++++---------- 2 files changed, 18 insertions(+), 20 deletions(-) diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 952054a3fd6..979ba1638d0 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -191,17 +191,16 @@ def FBO : FPBranchV8<0b1111, "fbo">; // Section B.24 - Call and Link Instruction, p. 125 // This is the only Format 1 instruction -def CALL : InstV8 { - bits<30> disp; - let op = 1; - let Inst{29-0} = disp; - let Name = "call"; - let isCall = 1; -} - -// Section B.25 - Jump and Link, p. 126 -let isCall = 1 in +let Defs = [O0, O1, O2, O3, O4, O5] in +let isCall = 1 in { + def CALL : InstV8 { + bits<30> disp; + let op = 1; + let Inst{29-0} = disp; + let Name = "call"; + } def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd +} // Section B.29 - Write State Register Instructions def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.td b/lib/Target/SparcV8/SparcV8InstrInfo.td index 952054a3fd6..979ba1638d0 100644 --- a/lib/Target/SparcV8/SparcV8InstrInfo.td +++ b/lib/Target/SparcV8/SparcV8InstrInfo.td @@ -191,17 +191,16 @@ def FBO : FPBranchV8<0b1111, "fbo">; // Section B.24 - Call and Link Instruction, p. 125 // This is the only Format 1 instruction -def CALL : InstV8 { - bits<30> disp; - let op = 1; - let Inst{29-0} = disp; - let Name = "call"; - let isCall = 1; -} - -// Section B.25 - Jump and Link, p. 126 -let isCall = 1 in +let Defs = [O0, O1, O2, O3, O4, O5] in +let isCall = 1 in { + def CALL : InstV8 { + bits<30> disp; + let op = 1; + let Inst{29-0} = disp; + let Name = "call"; + } def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd +} // Section B.29 - Write State Register Instructions def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd