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80-column, tab characters, comment fixups.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207473 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
2014-04-29 00:16:40 +00:00
parent 4ffd83b92b
commit 3756feaadc
1 changed files with 44 additions and 43 deletions
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87
lib/Target/PowerPC/PPCFrameLowering.cpp
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@ -222,7 +222,7 @@ unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
if (!DisableRedZone && if (!DisableRedZone &&
(Subtarget.isPPC64() || // 32-bit SVR4, no stack- (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
!Subtarget.isSVR4ABI() || // allocated locals. !Subtarget.isSVR4ABI() || // allocated locals.
FrameSize == 0) && FrameSize == 0) &&
FrameSize <= 224 && // Fits in red zone. FrameSize <= 224 && // Fits in red zone.
!MFI->hasVarSizedObjects() && // No dynamic alloca. !MFI->hasVarSizedObjects() && // No dynamic alloca.
!MFI->adjustsStack() && // No calls. !MFI->adjustsStack() && // No calls.
@ -281,8 +281,8 @@ bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
// Naked functions have no stack frame pushed, so we don't have a frame // Naked functions have no stack frame pushed, so we don't have a frame
// pointer. // pointer.
if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex, if (MF.getFunction()->getAttributes().hasAttribute(
Attribute::Naked)) AttributeSet::FunctionIndex, Attribute::Naked))
return false; return false;
return MF.getTarget().Options.DisableFramePointerElim(MF) || return MF.getTarget().Options.DisableFramePointerElim(MF) ||
@ -426,7 +426,8 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
assert(FPIndex && "No Frame Pointer Save Slot!"); assert(FPIndex && "No Frame Pointer Save Slot!");
FPOffset = FFI->getObjectOffset(FPIndex); FPOffset = FFI->getObjectOffset(FPIndex);
} else { } else {
FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); FPOffset =
PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
} }
} }
@ -712,7 +713,8 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
assert(FPIndex && "No Frame Pointer Save Slot!"); assert(FPIndex && "No Frame Pointer Save Slot!");
FPOffset = FFI->getObjectOffset(FPIndex); FPOffset = FFI->getObjectOffset(FPIndex);
} else { } else {
FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); FPOffset =
PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
} }
} }
@ -930,9 +932,9 @@ PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
} }
// For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
// function uses CR 2, 3, or 4. // function uses CR 2, 3, or 4.
if (!isPPC64 && !isDarwinABI && if (!isPPC64 && !isDarwinABI &&
(MRI.isPhysRegUsed(PPC::CR2) || (MRI.isPhysRegUsed(PPC::CR2) ||
MRI.isPhysRegUsed(PPC::CR3) || MRI.isPhysRegUsed(PPC::CR3) ||
MRI.isPhysRegUsed(PPC::CR4))) { MRI.isPhysRegUsed(PPC::CR4))) {
@ -1106,10 +1108,10 @@ void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
unsigned Reg = CSI[i].getReg(); unsigned Reg = CSI[i].getReg();
if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2) if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
// Leave Darwin logic as-is. // Leave Darwin logic as-is.
|| (!Subtarget.isSVR4ABI() && || (!Subtarget.isSVR4ABI() &&
(PPC::CRBITRCRegClass.contains(Reg) || (PPC::CRBITRCRegClass.contains(Reg) ||
PPC::CRRCRegClass.contains(Reg)))) { PPC::CRRCRegClass.contains(Reg)))) {
int FI = CSI[i].getFrameIdx(); int FI = CSI[i].getFrameIdx();
FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
@ -1190,11 +1192,11 @@ PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
} }
} }
bool bool
PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI, const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const { const TargetRegisterInfo *TRI) const {
// Currently, this function only handles SVR4 32- and 64-bit ABIs. // Currently, this function only handles SVR4 32- and 64-bit ABIs.
// Return false otherwise to maintain pre-existing behavior. // Return false otherwise to maintain pre-existing behavior.
@ -1207,7 +1209,7 @@ PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
DebugLoc DL; DebugLoc DL;
bool CRSpilled = false; bool CRSpilled = false;
MachineInstrBuilder CRMIB; MachineInstrBuilder CRMIB;
for (unsigned i = 0, e = CSI.size(); i != e; ++i) { for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
unsigned Reg = CSI[i].getReg(); unsigned Reg = CSI[i].getReg();
// Only Darwin actually uses the VRSAVE register, but it can still appear // Only Darwin actually uses the VRSAVE register, but it can still appear
@ -1237,21 +1239,21 @@ PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
CRSpilled = true; CRSpilled = true;
FuncInfo->setSpillsCR(); FuncInfo->setSpillsCR();
// 32-bit: FP-relative. Note that we made sure CR2-CR4 all have // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
// the same frame index in PPCRegisterInfo::hasReservedSpillSlot. // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12) CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
.addReg(Reg, RegState::ImplicitKill); .addReg(Reg, RegState::ImplicitKill);
MBB.insert(MI, CRMIB); MBB.insert(MI, CRMIB);
MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW)) MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
.addReg(PPC::R12, .addReg(PPC::R12,
getKillRegState(true)), getKillRegState(true)),
CSI[i].getFrameIdx())); CSI[i].getFrameIdx()));
} }
} else { } else {
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
TII.storeRegToStackSlot(MBB, MI, Reg, true, TII.storeRegToStackSlot(MBB, MI, Reg, true,
CSI[i].getFrameIdx(), RC, TRI); CSI[i].getFrameIdx(), RC, TRI);
} }
} }
return true; return true;
@ -1260,8 +1262,8 @@ PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
static void static void
restoreCRs(bool isPPC64, bool is31, restoreCRs(bool isPPC64, bool is31,
bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) { const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
MachineFunction *MF = MBB.getParent(); MachineFunction *MF = MBB.getParent();
const PPCInstrInfo &TII = const PPCInstrInfo &TII =
@ -1275,12 +1277,12 @@ restoreCRs(bool isPPC64, bool is31,
else { else {
// 32-bit: FP-relative // 32-bit: FP-relative
MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
PPC::R12), PPC::R12),
CSI[CSIIndex].getFrameIdx())); CSI[CSIIndex].getFrameIdx()));
RestoreOp = PPC::MTOCRF; RestoreOp = PPC::MTOCRF;
MoveReg = PPC::R12; MoveReg = PPC::R12;
} }
if (CR2Spilled) if (CR2Spilled)
MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2) MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
.addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled))); .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
@ -1335,11 +1337,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MBB.erase(I); MBB.erase(I);
} }
bool bool
PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI, const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const { const TargetRegisterInfo *TRI) const {
// Currently, this function only handles SVR4 32- and 64-bit ABIs. // Currently, this function only handles SVR4 32- and 64-bit ABIs.
// Return false otherwise to maintain pre-existing behavior. // Return false otherwise to maintain pre-existing behavior.
@ -1387,20 +1389,20 @@ PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
// When we first encounter a non-CR register after seeing at // When we first encounter a non-CR register after seeing at
// least one CR register, restore all spilled CRs together. // least one CR register, restore all spilled CRs together.
if ((CR2Spilled || CR3Spilled || CR4Spilled) if ((CR2Spilled || CR3Spilled || CR4Spilled)
&& !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) { && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
bool is31 = needsFP(*MF); bool is31 = needsFP(*MF);
restoreCRs(Subtarget.isPPC64(), is31, restoreCRs(Subtarget.isPPC64(), is31,
CR2Spilled, CR3Spilled, CR4Spilled, CR2Spilled, CR3Spilled, CR4Spilled,
MBB, I, CSI, CSIIndex); MBB, I, CSI, CSIIndex);
CR2Spilled = CR3Spilled = CR4Spilled = false; CR2Spilled = CR3Spilled = CR4Spilled = false;
} }
// Default behavior for non-CR saves. // Default behavior for non-CR saves.
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(), TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
RC, TRI); RC, TRI);
assert(I != MBB.begin() && assert(I != MBB.begin() &&
"loadRegFromStackSlot didn't insert any code!"); "loadRegFromStackSlot didn't insert any code!");
} }
// Insert in reverse order. // Insert in reverse order.
@ -1409,16 +1411,15 @@ PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
else { else {
I = BeforeI; I = BeforeI;
++I; ++I;
} }
} }
// If we haven't yet spilled the CRs, do so now. // If we haven't yet spilled the CRs, do so now.
if (CR2Spilled || CR3Spilled || CR4Spilled) { if (CR2Spilled || CR3Spilled || CR4Spilled) {
bool is31 = needsFP(*MF); bool is31 = needsFP(*MF);
restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled, restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
MBB, I, CSI, CSIIndex); MBB, I, CSI, CSIIndex);
} }
return true; return true;
} }