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https://github.com/c64scene-ar/llvm-6502.git
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Merge 128-bit and 256-bit X86ISD node types for VPERMILPS and VPERMILPD. Simplify some shuffle lowering code since V1 can never be UNDEF due to canonalizing that occurs when shuffle nodes are created.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145153 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
a18f08318a
commit
38034c568c
@ -2848,9 +2848,7 @@ static bool isTargetShuffle(unsigned Opcode) {
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case X86ISD::UNPCKHP:
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case X86ISD::PUNPCKH:
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case X86ISD::VPERMILPS:
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case X86ISD::VPERMILPSY:
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case X86ISD::VPERMILPD:
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case X86ISD::VPERMILPDY:
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case X86ISD::VPERM2F128:
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return true;
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}
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@ -2878,9 +2876,7 @@ static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
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case X86ISD::PSHUFHW:
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case X86ISD::PSHUFLW:
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case X86ISD::VPERMILPS:
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case X86ISD::VPERMILPSY:
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case X86ISD::VPERMILPD:
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case X86ISD::VPERMILPDY:
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return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
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}
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@ -4664,22 +4660,12 @@ static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
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}
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case X86ISD::VPERMILPS:
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ImmN = N->getOperand(N->getNumOperands()-1);
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DecodeVPERMILPSMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
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ShuffleMask);
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break;
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case X86ISD::VPERMILPSY:
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ImmN = N->getOperand(N->getNumOperands()-1);
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DecodeVPERMILPSMask(8, cast<ConstantSDNode>(ImmN)->getZExtValue(),
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DecodeVPERMILPSMask(NumElems, cast<ConstantSDNode>(ImmN)->getZExtValue(),
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ShuffleMask);
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break;
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case X86ISD::VPERMILPD:
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ImmN = N->getOperand(N->getNumOperands()-1);
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DecodeVPERMILPDMask(2, cast<ConstantSDNode>(ImmN)->getZExtValue(),
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ShuffleMask);
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break;
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case X86ISD::VPERMILPDY:
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ImmN = N->getOperand(N->getNumOperands()-1);
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DecodeVPERMILPDMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
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DecodeVPERMILPDMask(NumElems, cast<ConstantSDNode>(ImmN)->getZExtValue(),
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ShuffleMask);
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break;
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case X86ISD::VPERM2F128:
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@ -6589,13 +6575,13 @@ static inline unsigned getUNPCKHOpcode(EVT VT, bool HasAVX2) {
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static inline unsigned getVPERMILOpcode(EVT VT) {
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switch(VT.getSimpleVT().SimpleTy) {
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case MVT::v4i32:
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case MVT::v4f32: return X86ISD::VPERMILPS;
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case MVT::v2i64:
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case MVT::v2f64: return X86ISD::VPERMILPD;
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case MVT::v4f32:
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case MVT::v8i32:
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case MVT::v8f32: return X86ISD::VPERMILPSY;
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case MVT::v8f32: return X86ISD::VPERMILPS;
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case MVT::v2i64:
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case MVT::v2f64:
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case MVT::v4i64:
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case MVT::v4f64: return X86ISD::VPERMILPDY;
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case MVT::v4f64: return X86ISD::VPERMILPD;
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default:
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llvm_unreachable("Unknown type for vpermil");
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}
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@ -6675,7 +6661,6 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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EVT VT = Op.getValueType();
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DebugLoc dl = Op.getDebugLoc();
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unsigned NumElems = VT.getVectorNumElements();
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bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
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bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
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bool V1IsSplat = false;
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bool V2IsSplat = false;
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@ -6686,6 +6671,8 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
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assert(V1.getOpcode() != ISD::UNDEF && "Op 1 of shuffle should not be undef");
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// Vector shuffle lowering takes 3 steps:
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//
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// 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
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@ -6759,8 +6746,6 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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}
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if (X86::isMOVLMask(SVOp)) {
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if (V1IsUndef)
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return V2;
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if (ISD::isBuildVectorAllZeros(V1.getNode()))
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return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
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if (!X86::isMOVLPMask(SVOp)) {
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@ -6806,13 +6791,12 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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V2IsSplat = isSplatVector(V2.getNode());
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// Canonicalize the splat or undef, if present, to be on the RHS.
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if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
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if (V1IsSplat && !V2IsSplat) {
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Op = CommuteVectorShuffle(SVOp, DAG);
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SVOp = cast<ShuffleVectorSDNode>(Op);
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V1 = SVOp->getOperand(0);
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V2 = SVOp->getOperand(1);
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std::swap(V1IsSplat, V2IsSplat);
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std::swap(V1IsUndef, V2IsUndef);
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Commuted = true;
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}
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@ -6865,7 +6849,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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}
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// Normalize the node to match x86 shuffle ops if needed
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if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
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if (!V2IsUndef && isCommutedSHUFP(SVOp))
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return CommuteVectorShuffle(SVOp, DAG);
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// The checks below are all present in isShuffleMaskLegal, but they are
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@ -11244,9 +11228,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::PUNPCKH: return "X86ISD::PUNPCKH";
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case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
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case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS";
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case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY";
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case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD";
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case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY";
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case X86ISD::VPERM2F128: return "X86ISD::VPERM2F128";
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case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
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case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
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@ -14833,9 +14815,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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case X86ISD::MOVSS:
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case X86ISD::MOVSD:
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case X86ISD::VPERMILPS:
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case X86ISD::VPERMILPSY:
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case X86ISD::VPERMILPD:
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case X86ISD::VPERMILPDY:
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case X86ISD::VPERM2F128:
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case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
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}
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@ -278,9 +278,7 @@ namespace llvm {
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PUNPCKL,
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PUNPCKH,
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VPERMILPS,
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VPERMILPSY,
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VPERMILPD,
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VPERMILPDY,
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VPERM2F128,
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VBROADCAST,
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@ -137,9 +137,7 @@ def X86Punpckl : SDNode<"X86ISD::PUNPCKL", SDTShuff2Op>;
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def X86Punpckh : SDNode<"X86ISD::PUNPCKH", SDTShuff2Op>;
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def X86VPermilps : SDNode<"X86ISD::VPERMILPS", SDTShuff2OpI>;
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def X86VPermilpsy : SDNode<"X86ISD::VPERMILPSY", SDTShuff2OpI>;
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def X86VPermilpd : SDNode<"X86ISD::VPERMILPD", SDTShuff2OpI>;
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def X86VPermilpdy : SDNode<"X86ISD::VPERMILPDY", SDTShuff2OpI>;
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def X86VPerm2f128 : SDNode<"X86ISD::VPERM2F128", SDTShuff3OpI>;
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@ -7321,13 +7321,13 @@ let ExeDomain = SSEPackedDouble in {
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int_x86_avx_vpermil_pd_256>;
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}
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def : Pat<(v8f32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
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def : Pat<(v8f32 (X86VPermilps VR256:$src1, (i8 imm:$imm))),
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(VPERMILPSYri VR256:$src1, imm:$imm)>;
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def : Pat<(v4f64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
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def : Pat<(v4f64 (X86VPermilpd VR256:$src1, (i8 imm:$imm))),
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(VPERMILPDYri VR256:$src1, imm:$imm)>;
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def : Pat<(v8i32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
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def : Pat<(v8i32 (X86VPermilps VR256:$src1, (i8 imm:$imm))),
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(VPERMILPSYri VR256:$src1, imm:$imm)>;
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def : Pat<(v4i64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
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def : Pat<(v4i64 (X86VPermilpd VR256:$src1, (i8 imm:$imm))),
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(VPERMILPDYri VR256:$src1, imm:$imm)>;
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//===----------------------------------------------------------------------===//
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