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For PR950:
This patch converts the old SHR instruction into two instructions, AShr (Arithmetic) and LShr (Logical). The Shr instructions now are not dependent on the sign of their operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31542 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -719,7 +719,15 @@ BytecodeReader::handleObsoleteOpcodes(
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Opcode = Instruction::Shl;
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break;
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case 31: // Shr
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Opcode = Instruction::Shr;
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// The type of the instruction is based on the operands. We need to
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// select ashr or lshr based on that type. The iType values are hardcoded
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// to the values used in bytecode version 5 (and prior) because it is
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// likely these codes will change in future versions of LLVM. This if
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// statement says "if (integer type and signed)"
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if (iType >= 2 && iType <= 9 && iType % 2 != 0)
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Opcode = Instruction::AShr;
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else
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Opcode = Instruction::LShr;
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break;
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case 32: { //VANext_old ( <= llvm 1.5 )
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const Type* ArgTy = getValue(iType, Oprnds[0])->getType();
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@ -987,7 +995,8 @@ void BytecodeReader::ParseInstruction(std::vector<unsigned> &Oprnds,
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}
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case Instruction::Shl:
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case Instruction::Shr:
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case Instruction::LShr:
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case Instruction::AShr:
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Result = new ShiftInst(Instruction::OtherOps(Opcode),
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getValue(iType, Oprnds[0]),
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getValue(Type::UByteTyID, Oprnds[1]));
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@ -1707,7 +1716,10 @@ inline unsigned fixCEOpcodes(
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Opcode = Instruction::Shl;
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break;
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case 31: // Shr
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Opcode = Instruction::Shr;
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if (ArgVec[0]->getType()->isSigned())
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Opcode = Instruction::AShr;
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else
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Opcode = Instruction::LShr;
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break;
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case 34: // Select
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Opcode = Instruction::Select;
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