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Thumb assembly parsing and encoding for LDRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138060 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -169,11 +169,13 @@ def t_addrmode_is4 : Operand<i32>,
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// t_addrmode_is2 := reg + imm5 * 2
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//
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def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
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def t_addrmode_is2 : Operand<i32>,
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ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
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let EncoderMethod = "getAddrModeISOpValue";
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let DecoderMethod = "DecodeThumbAddrModeIS";
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let PrintMethod = "printThumbAddrModeImm5S2Operand";
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let ParserMatchClass = t_addrmode_is2_asm_operand;
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let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
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}
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@ -628,6 +628,15 @@ public:
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int64_t Val = Mem.OffsetImm->getValue();
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return Val >= 0 && Val <= 124 && (Val % 4) == 0;
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}
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bool isMemThumbRIs2() const {
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if (Kind != Memory || Mem.OffsetRegNum != 0 ||
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!isARMLowRegister(Mem.BaseRegNum))
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return false;
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// Immediate offset, multiple of 4 in range [0, 62].
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if (!Mem.OffsetImm) return true;
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int64_t Val = Mem.OffsetImm->getValue();
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return Val >= 0 && Val <= 62 && (Val % 2) == 0;
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}
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bool isMemThumbRIs1() const {
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if (Kind != Memory || Mem.OffsetRegNum != 0 ||
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!isARMLowRegister(Mem.BaseRegNum))
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@ -1009,6 +1018,13 @@ public:
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Inst.addOperand(MCOperand::CreateImm(Val));
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}
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void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
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assert(N == 2 && "Invalid number of operands!");
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int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
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Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
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Inst.addOperand(MCOperand::CreateImm(Val));
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}
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void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
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assert(N == 2 && "Invalid number of operands!");
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int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
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@ -230,3 +230,23 @@ _func:
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ldrb r6, [r4, r5]
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@ CHECK: ldrb r6, [r4, r5] @ encoding: [0x66,0x5d]
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@------------------------------------------------------------------------------
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@ LDRH (immediate)
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@------------------------------------------------------------------------------
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ldrh r3, [r3]
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ldrh r4, [r6, #2]
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ldrh r5, [r7, #62]
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@ CHECK: ldrh r3, [r3] @ encoding: [0x1b,0x88]
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@ CHECK: ldrh r4, [r6, #2] @ encoding: [0x74,0x88]
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@ CHECK: ldrh r5, [r7, #62] @ encoding: [0xfd,0x8f]
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@------------------------------------------------------------------------------
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@ LDRH (register)
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@------------------------------------------------------------------------------
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ldrh r6, [r2, r6]
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@ CHECK: ldrh r6, [r2, r6] @ encoding: [0x96,0x5b]
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