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https://github.com/c64scene-ar/llvm-6502.git
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AVX-512: Added more patterns for VMOVSS, VMOVSD, VMOVD, VMOVQ
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188786 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
c5158b869b
commit
38cd21a3e9
@ -1305,28 +1305,51 @@ let isCodeGenOnly = 1 in {
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}
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let Predicates = [HasAVX512] in {
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let AddedComplexity = 15 in {
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// Move scalar to XMM zero-extended, zeroing a VR128X then do a
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// MOVS{S,D} to the lower bits.
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def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
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(VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
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def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
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(VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
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def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
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(VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
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def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
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(VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
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// Move low f32 and clear high bits.
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def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
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(SUBREG_TO_REG (i32 0),
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(VMOVSSZrr (v4f32 (V_SET0)),
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(EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
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def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
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(SUBREG_TO_REG (i32 0),
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(VMOVSSZrr (v4i32 (V_SET0)),
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(EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
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}
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let AddedComplexity = 20 in {
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// MOVSSrm zeros the high parts of the register; represent this
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// with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
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def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
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(COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128X)>;
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(COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
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def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
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(COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128X)>;
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(COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
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def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
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(COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128X)>;
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(COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
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// MOVSDrm zeros the high parts of the register; represent this
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// with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
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def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
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(COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128X)>;
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(COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
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def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
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(COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128X)>;
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(COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
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def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
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(COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128X)>;
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(COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
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def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
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(COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128X)>;
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(COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
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def : Pat<(v2f64 (X86vzload addr:$src)),
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(COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128X)>;
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(COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
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// Represent the same patterns above but in the form they appear for
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// 256-bit types
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@ -1340,10 +1363,28 @@ let Predicates = [HasAVX512] in {
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(v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
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(SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
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}
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def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
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(v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
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(SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
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FR32X:$src)), sub_xmm)>;
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def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
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(v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
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(SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
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FR64X:$src)), sub_xmm)>;
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def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
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(v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
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(SUBREG_TO_REG (i64 0), (VMOVSDZrm addr:$src), sub_xmm)>;
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// Move low f64 and clear high bits.
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def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
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(SUBREG_TO_REG (i32 0),
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(VMOVSDZrr (v2f64 (V_SET0)),
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(EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
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def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
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(SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
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(EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
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// Extract and store.
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def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
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addr:$dst),
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@ -1420,11 +1461,29 @@ def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
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(loadv2i64 addr:$src))))],
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IIC_SSE_MOVDQ>, EVEX, VEX_W,
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EVEX_CD8<8, CD8VT8>;
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let AddedComplexity = 20 in {
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def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
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let Predicates = [HasAVX512] in {
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// AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
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let AddedComplexity = 20 in {
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def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
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(VMOVDI2PDIZrm addr:$src)>;
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def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
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(VMOVDI2PDIZrm addr:$src)>;
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def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
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(VMOVDI2PDIZrm addr:$src)>;
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def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
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(VMOVZPQILo2PQIZrm addr:$src)>;
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def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
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def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
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(VMOVZPQILo2PQIZrr VR128X:$src)>;
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}
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// Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
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def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
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(v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
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(SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
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def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
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(v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
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(SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
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}
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//===----------------------------------------------------------------------===//
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@ -526,7 +526,7 @@ let canFoldAsLoad = 1, isReMaterializable = 1 in {
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}
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// Patterns
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let Predicates = [HasAVX] in {
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let Predicates = [UseAVX] in {
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let AddedComplexity = 15 in {
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// Move scalar to XMM zero-extended, zeroing a VR128 then do a
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// MOVS{S,D} to the lower bits.
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@ -73,3 +73,30 @@ define i64 @test9(<2 x i64> %x) {
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%res = extractelement <2 x i64> %x, i32 0
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ret i64 %res
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}
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; CHECK-LABEL: @test10
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; CHECK: vmovdz (%rdi)
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; CHECK: ret
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define <4 x i32> @test10(i32* %x) {
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%y = load i32* %x, align 4
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%res = insertelement <4 x i32>zeroinitializer, i32 %y, i32 0
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ret <4 x i32>%res
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}
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; CHECK-LABEL: @test11
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; CHECK: vmovssz (%rdi)
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; CHECK: ret
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define <4 x float> @test11(float* %x) {
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%y = load float* %x, align 4
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%res = insertelement <4 x float>zeroinitializer, float %y, i32 0
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ret <4 x float>%res
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}
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; CHECK-LABEL: @test12
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; CHECK: vmovsdz (%rdi)
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; CHECK: ret
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define <2 x double> @test12(double* %x) {
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%y = load double* %x, align 8
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%res = insertelement <2 x double>zeroinitializer, double %y, i32 0
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ret <2 x double>%res
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}
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