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TargetSchedule: cleanup computeOperandLatency logic & diagnostics.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164154 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-09-18 18:20:02 +00:00
parent 781ab4777f
commit 3918cade8f
1 changed files with 16 additions and 6 deletions
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22
lib/CodeGen/TargetSchedule.cpp
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@ -17,6 +17,7 @@
#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h" #include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm; using namespace llvm;
@ -98,11 +99,15 @@ static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx) {
/// Find the use index of this operand. This is independent of the instruction's /// Find the use index of this operand. This is independent of the instruction's
/// def operands. /// def operands.
///
/// Note that uses are not determined by the operand's isUse property, which
/// is simply the inverse of isDef. Here we consider any readsReg operand to be
/// a "use". The machine model allows an operand to be both a Def and Use.
static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) { static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) {
unsigned UseIdx = 0; unsigned UseIdx = 0;
for (unsigned i = 0; i != UseOperIdx; ++i) { for (unsigned i = 0; i != UseOperIdx; ++i) {
const MachineOperand &MO = MI->getOperand(i); const MachineOperand &MO = MI->getOperand(i);
if (MO.isReg() && MO.isUse()) if (MO.isReg() && MO.readsReg())
++UseIdx; ++UseIdx;
} }
return UseIdx; return UseIdx;
@ -122,7 +127,6 @@ unsigned TargetSchedModel::computeOperandLatency(
const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
if (DefIdx < SCDesc->NumWriteLatencyEntries) { if (DefIdx < SCDesc->NumWriteLatencyEntries) {
// Lookup the definition's write latency in SubtargetInfo. // Lookup the definition's write latency in SubtargetInfo.
const MCWriteLatencyEntry *WLEntry = const MCWriteLatencyEntry *WLEntry =
STI->getWriteLatencyEntry(SCDesc, DefIdx); STI->getWriteLatencyEntry(SCDesc, DefIdx);
@ -140,10 +144,16 @@ unsigned TargetSchedModel::computeOperandLatency(
} }
// If DefIdx does not exist in the model (e.g. implicit defs), then return // If DefIdx does not exist in the model (e.g. implicit defs), then return
// unit latency (defaultDefLatency may be too conservative). // unit latency (defaultDefLatency may be too conservative).
// TODO: For unknown defs, we may want to use the subtarget's model #ifndef NDEBUG
// for WAW latency here instead of 1 cycle. if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
assert((!SCDesc->isValid() || DefMI->getOperand(DefOperIdx).isImplicit()) && && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()) {
"DefIdx exceeds machine model def operand list"); std::string Err;
raw_string_ostream ss(Err);
ss << "DefIdx " << DefIdx << " exceeds machine model writes for "
<< *DefMI;
report_fatal_error(ss.str());
}
#endif
return 1; return 1;
} }
assert(EnableSchedItins && hasInstrItineraries() && assert(EnableSchedItins && hasInstrItineraries() &&