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Switch all register list clients to the new MC*Iterator interface.

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No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.

This makes it possible to do so without changing all clients (again).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157854 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2012-06-01 23:28:30 +00:00
parent 4a8fefaf83
commit 396618b43a
35 changed files with 199 additions and 221 deletions
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8
lib/CodeGen/RegAllocBasic.cpp
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@@ -204,8 +204,8 @@ bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
// either the union or live intervals.
unsigned NumInterferences = 0;
// Collect interferences assigned to any alias of the physical register.
for (const uint16_t *asI = TRI->getOverlaps(PhysReg); *asI; ++asI) {
LiveIntervalUnion::Query &QAlias = query(VirtReg, *asI);
for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
LiveIntervalUnion::Query &QAlias = query(VirtReg, *AI);
NumInterferences += QAlias.collectInterferingVRegs();
if (QAlias.seenUnspillableVReg()) {
return false;
@@ -216,8 +216,8 @@ bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
assert(NumInterferences > 0 && "expect interference");
// Spill each interfering vreg allocated to PhysReg or an alias.
for (const uint16_t *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI)
spillReg(VirtReg, *AliasI, SplitVRegs);
for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI)
spillReg(VirtReg, *AI, SplitVRegs);
return true;
}