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ARM assembly parsing and encoding for VLD1 with writeback.

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Four entry register lists.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142882 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-10-25 00:14:01 +00:00
parent 3e6157de57
commit 399cdca4d2
4 changed files with 53 additions and 17 deletions
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12
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -2078,10 +2078,14 @@ static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
case ARM::VLD1d32Twb_register:
case ARM::VLD1d64Twb_fixed:
case ARM::VLD1d64Twb_register:
case ARM::VLD1d8Q_UPD:
case ARM::VLD1d16Q_UPD:
case ARM::VLD1d32Q_UPD:
case ARM::VLD1d64Q_UPD:
case ARM::VLD1d8Qwb_fixed:
case ARM::VLD1d8Qwb_register:
case ARM::VLD1d16Qwb_fixed:
case ARM::VLD1d16Qwb_register:
case ARM::VLD1d32Qwb_fixed:
case ARM::VLD1d32Qwb_register:
case ARM::VLD1d64Qwb_fixed:
case ARM::VLD1d64Qwb_register:
case ARM::VLD2d8_UPD:
case ARM::VLD2d16_UPD:
case ARM::VLD2d32_UPD: