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Add emitInstruction() API so that we can get the bytes of a simple instruction

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12252 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alkis Evlogimenos 2004-03-09 03:34:53 +00:00
parent f6e8156008
commit 39c2005b70
2 changed files with 20 additions and 3 deletions
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16
lib/Target/X86/X86CodeEmitter.cpp
View File

@ -168,7 +168,6 @@ unsigned JITResolver::emitStubForFunction(Function *F) {
}
namespace {
class Emitter : public MachineFunctionPass {
const X86InstrInfo *II;
@ -176,7 +175,9 @@ namespace {
std::map<const BasicBlock*, unsigned> BasicBlockAddrs;
std::vector<std::pair<const BasicBlock*, unsigned> > BBRefs;
public:
Emitter(MachineCodeEmitter &mce) : II(0), MCE(mce) {}
explicit Emitter(MachineCodeEmitter &mce) : II(0), MCE(mce) {}
Emitter(MachineCodeEmitter &mce, const X86InstrInfo& ii)
: II(&ii), MCE(mce) {}
bool runOnMachineFunction(MachineFunction &MF);
@ -184,9 +185,10 @@ namespace {
return "X86 Machine Code Emitter";
}
void emitInstruction(const MachineInstr &MI);
private:
void emitBasicBlock(const MachineBasicBlock &MBB);
void emitInstruction(const MachineInstr &MI);
void emitPCRelativeBlockAddress(const BasicBlock *BB);
void emitMaybePCRelativeValue(unsigned Address, bool isPCRelative);
@ -203,6 +205,14 @@ namespace {
};
}
// This function is required by Printer.cpp to workaround gas bugs
void llvm::X86::emitInstruction(MachineCodeEmitter& mce,
const X86InstrInfo& ii,
const MachineInstr& mi)
{
Emitter(mce, ii).emitInstruction(mi);
}
/// addPassesToEmitMachineCode - Add passes to the specified pass manager to get
/// machine code emitted. This uses a MachineCodeEmitter object to handle
/// actually outputting the machine code and resolving things like the address

7
lib/Target/X86/X86TargetMachine.h
View File

@ -53,6 +53,13 @@ public:
virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
};
// this is implemented in X86CodeEmitter.cpp
namespace X86 {
void emitInstruction(MachineCodeEmitter& mce,
const X86InstrInfo& ii,
const MachineInstr& MI);
}
} // End llvm namespace
#endif